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Adding hw_en pin to SPI module

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- b/c there are times when you need physical control of the pins (can't do it in software, no packets will arrive)
- use case examples: security, power gating, reliability
This commit is contained in:
Andreas Olofsson 2016-03-30 12:02:05 -04:00
parent ab19abd965
commit 4f5b3ab8a9
8 changed files with 62 additions and 44 deletions
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16
src/spi/hdl/spi.v
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@ -10,8 +10,8 @@ module spi (/*AUTOARG*/
spi_irq, access_out, packet_out, wait_out, m_sclk, m_mosi, m_ss,
s_miso,
// Inputs
nreset, clk, master_mode, access_in, packet_in, wait_in, m_miso,
s_sclk, s_mosi, s_ss
nreset, clk, hw_en, access_in, packet_in, wait_in, m_miso, s_sclk,
s_mosi, s_ss
);
//##################################################################
@ -23,10 +23,10 @@ module spi (/*AUTOARG*/
parameter UREGS = 13; // number of user slave regs
//clk, reset, irq
input nreset; // asynch active low reset
input clk; // core clock
input master_mode;// master mode selector
input nreset; // asynch active low reset
input clk; // core clock
input hw_en; // block enable pin
//interrupt output
output spi_irq; // interrupt output
@ -72,6 +72,7 @@ module spi (/*AUTOARG*/
/*spi_master AUTO_TEMPLATE (.clk (clk),
.nreset (nreset),
.hw_en (hw_en),
.\(.*\)_in (\1_in[]),
.\(.*\) (m_\1[]),
);
@ -89,6 +90,7 @@ module spi (/*AUTOARG*/
// Inputs
.clk (clk), // Templated
.nreset (nreset), // Templated
.hw_en (hw_en), // Templated
.miso (m_miso), // Templated
.access_in (access_in), // Templated
.packet_in (packet_in[PW-1:0]), // Templated
@ -101,6 +103,7 @@ module spi (/*AUTOARG*/
/*spi_slave AUTO_TEMPLATE (.clk (clk),
.spi_irq (spi_irq),
.nreset (nreset),
.hw_en (hw_en),
.\(.*\)_in (\1_in[]),
.\(.*\) (s_\1[]),
);
@ -119,6 +122,7 @@ module spi (/*AUTOARG*/
// Inputs
.clk (clk), // Templated
.nreset (nreset), // Templated
.hw_en (hw_en), // Templated
.sclk (s_sclk), // Templated
.mosi (s_mosi), // Templated
.ss (s_ss), // Templated

9
src/spi/hdl/spi_master.v
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@ -9,7 +9,7 @@ module spi_master(/*AUTOARG*/
// Outputs
sclk, mosi, ss, wait_out, access_out, packet_out,
// Inputs
clk, nreset, miso, access_in, packet_in, wait_in
clk, nreset, hw_en, miso, access_in, packet_in, wait_in
);
//parameters
@ -21,6 +21,7 @@ module spi_master(/*AUTOARG*/
//clk,reset, cfg
input clk; // core clock
input nreset; // async active low reset
input hw_en; // hardware enable pin
//IO interface
output sclk; // spi clock
@ -80,6 +81,7 @@ module spi_master(/*AUTOARG*/
// Inputs
.clk (clk),
.nreset (nreset),
.hw_en (hw_en),
.rx_data (rx_data[63:0]),
.rx_access (rx_access),
.spi_state (spi_state[1:0]),
@ -100,7 +102,8 @@ module spi_master(/*AUTOARG*/
spi_master_fifo #(.AW(AW),
.DEPTH(DEPTH))
spi_master_fifo(/*AUTOINST*/
spi_master_fifo(
/*AUTOINST*/
// Outputs
.fifo_prog_full (fifo_prog_full),
.wait_out (fifo_wait), // Templated
@ -109,6 +112,7 @@ module spi_master(/*AUTOARG*/
// Inputs
.clk (clk),
.nreset (nreset),
.spi_en (spi_en),
.emode (emode),
.access_in (access_in),
.packet_in (packet_in[PW-1:0]),
@ -131,7 +135,6 @@ module spi_master(/*AUTOARG*/
// Inputs
.clk (clk),
.nreset (nreset),
.spi_en (spi_en),
.cpol (cpol),
.cpha (cpha),
.lsbfirst (lsbfirst),

6
src/spi/hdl/spi_master_fifo.v
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@ -3,7 +3,7 @@ module spi_master_fifo (/*AUTOARG*/
// Outputs
fifo_prog_full, wait_out, fifo_empty, fifo_dout,
// Inputs
clk, nreset, emode, access_in, packet_in, fifo_read
clk, nreset, spi_en, emode, access_in, packet_in, fifo_read
);
//#####################################################################
//# INTERFACE
@ -20,6 +20,7 @@ module spi_master_fifo (/*AUTOARG*/
//clk,reset, cfg
input clk; // clk
input nreset; // async active low reset
input spi_en; // spi enable
input emode; // epiphany transfer mode
output fifo_prog_full; // fifo full indicator for status
@ -72,7 +73,8 @@ module spi_master_fifo (/*AUTOARG*/
((1<<datamode_in[1:0]));
assign tx_write = write_in &
assign tx_write = spi_en &
write_in &
access_in &
(dstaddr_in[5:0]==`SPI_TX);

8
src/spi/hdl/spi_master_io.v
View File

@ -9,8 +9,8 @@ module spi_master_io(/*AUTOARG*/
// Outputs
spi_state, fifo_read, rx_data, rx_access, sclk, mosi, ss,
// Inputs
clk, nreset, spi_en, cpol, cpha, lsbfirst, clkdiv_reg, cmd_reg,
emode, fifo_dout, fifo_empty, miso
clk, nreset, cpol, cpha, lsbfirst, clkdiv_reg, cmd_reg, emode,
fifo_dout, fifo_empty, miso
);
//#################################
@ -27,7 +27,6 @@ module spi_master_io(/*AUTOARG*/
input nreset; // async active low reset
//cfg
input spi_en; // spi enable
input cpol; // cpol
input cpha; // cpha
input lsbfirst; // send lsbfirst
@ -63,6 +62,7 @@ module spi_master_io(/*AUTOARG*/
wire clkfall1; // From oh_clockdiv of oh_clockdiv.v
wire clkout1; // From oh_clockdiv of oh_clockdiv.v
wire clkrise1; // From oh_clockdiv of oh_clockdiv.v
wire clkstable; // From oh_clockdiv of oh_clockdiv.v
// End of automatics
//#################################
@ -83,9 +83,11 @@ module spi_master_io(/*AUTOARG*/
.clkout1 (clkout1),
.clkrise1 (clkrise1),
.clkfall1 (clkfall1),
.clkstable (clkstable),
// Inputs
.clk (clk),
.nreset (nreset),
.clkchange (clkchange),
.clkphase0 (clkphase0[15:0]));
//#################################

19
src/spi/hdl/spi_master_regs.v
View File

@ -12,7 +12,7 @@ module spi_master_regs (/*AUTOARG*/
cpol, cpha, lsbfirst, emode, spi_en, clkdiv_reg, cmd_reg, wait_out,
access_out, packet_out,
// Inputs
clk, nreset, rx_data, rx_access, spi_state, fifo_prog_full,
clk, nreset, hw_en, rx_data, rx_access, spi_state, fifo_prog_full,
fifo_wait, access_in, packet_in, wait_in
);
@ -25,7 +25,8 @@ module spi_master_regs (/*AUTOARG*/
//clk,reset, cfg
input clk; // core clock
input nreset; // async active low reset
input hw_en; // block enable pin
//io interface
input [63:0] rx_data; // rx data
input rx_access; // rx access pulse
@ -118,13 +119,13 @@ module spi_master_regs (/*AUTOARG*/
else if(config_write)
config_reg[7:0] <= data_in[7:0];
assign spi_en = ~config_reg[0]; // disable spi (on by default)
assign irq_en = config_reg[1]; // enable interrupt
assign cpol = config_reg[2]; // cpol
assign cpha = config_reg[3]; // cpha
assign lsbfirst = config_reg[4]; // send lsb first
assign manual_ss = config_reg[5]; // manually control ss pin
assign emode = config_reg[6]; // epiphany transfer mode
assign spi_en = hw_en & ~config_reg[0]; // disable spi (on by default)
assign irq_en = config_reg[1]; // enable interrupt
assign cpol = config_reg[2]; // cpol
assign cpha = config_reg[3]; // cpha
assign lsbfirst = config_reg[4]; // send lsb first
assign manual_ss = config_reg[5]; // manually control ss pin
assign emode = config_reg[6]; // epiphany transfer mode
//####################################
//# STATUS

4
src/spi/hdl/spi_slave.v
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@ -9,7 +9,7 @@ module spi_slave(/*AUTOARG*/
// Outputs
spi_regs, spi_irq, miso, access_out, packet_out, wait_out,
// Inputs
clk, nreset, sclk, mosi, ss, wait_in, access_in, packet_in
clk, nreset, hw_en, sclk, mosi, ss, wait_in, access_in, packet_in
);
//parameters
@ -20,6 +20,7 @@ module spi_slave(/*AUTOARG*/
//clk,reset, cfg
input clk; // core clock
input nreset; // async active low reset
input hw_en; // block enbale pin
output [511:0] spi_regs; // all registers for control
output spi_irq; // interrupt
@ -75,6 +76,7 @@ module spi_slave(/*AUTOARG*/
// Inputs
.clk (clk),
.nreset (nreset),
.hw_en (hw_en),
.spi_clk (spi_clk),
.spi_wdata (spi_wdata[7:0]),
.spi_write (spi_write),

20
src/spi/hdl/spi_slave_io.v
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@ -102,6 +102,8 @@ module spi_slave_io(/*AUTOARG*/
//# RX SHIFT REGISTER
//#################################
assign rx_shift = ~ss & spi_en;
oh_ser2par #(.PW(8),
.SW(1))
ser2par (// Outputs
@ -110,14 +112,15 @@ module spi_slave_io(/*AUTOARG*/
.clk (sclk),
.din (mosi),
.lsbfirst (lsbfirst), //msb first
.shift (~ss)
.shift (rx_shift)
);
//#################################
//# TX SHIFT REGISTER
//#################################
assign tx_load = byte_done & (spi_state[1:0]==`SPI_CMD);
assign tx_load = byte_done & (spi_state[1:0]==`SPI_CMD);
assign tx_shift = ~ss & spi_en;
oh_par2ser #(.PW(8),
.SW(1))
@ -127,7 +130,7 @@ module spi_slave_io(/*AUTOARG*/
.clk (sclk), // shift out on positive edge
.nreset (~ss),
.din (spi_rdata[7:0]),
.shift (~ss),
.shift (tx_shift),
.lsbfirst (lsbfirst),
.load (tx_load),
.datasize (8'd7),
@ -143,13 +146,14 @@ module spi_slave_io(/*AUTOARG*/
assign spi_addr[5:0] = command_reg[5:0];
assign spi_write = byte_done &
assign spi_write = spi_en &
byte_done &
(command_reg[7:6]==2'b00) &
(spi_state[1:0]==`SPI_DATA);
assign spi_read = command_reg[7:6]==2'b10; //read from sclk reg
assign spi_remote = command_reg[7:6]==2'b11; //send remote request
assign spi_remote = spi_en &
ss & // wait until signal goes high
command_reg[7:6]==2'b11; // send remote request
assign spi_wdata[7:0] = rx_data[7:0];
@ -161,7 +165,7 @@ module spi_slave_io(/*AUTOARG*/
//look for rising edge
oh_dsync dsync (.dout (ss_sync),
.clk (clk),
.din (ss & spi_remote)
.din (spi_remote)
);
//create single cycle pulse

24
src/spi/hdl/spi_slave_regs.v
View File

@ -11,8 +11,8 @@ module spi_slave_regs (/*AUTOARG*/
spi_rdata, spi_en, cpol, cpha, lsbfirst, irq_en, emode, spi_regs,
wait_out,
// Inputs
clk, nreset, spi_clk, spi_wdata, spi_write, spi_addr, access_in,
packet_in
clk, nreset, hw_en, spi_clk, spi_wdata, spi_write, spi_addr,
access_in, packet_in
);
//parameters
@ -25,7 +25,8 @@ module spi_slave_regs (/*AUTOARG*/
// clk, rest, chipid
input clk; // core clock
input nreset; // asych active low
input hw_en; // block enable pin
// sclk io domain
input spi_clk; // slave clock
input [7:0] spi_wdata; // slave write data in (for write)
@ -95,8 +96,7 @@ module spi_slave_regs (/*AUTOARG*/
.packet_in (packet_in[PW-1:0]));
assign core_data[63:0]={srcaddr_in[31:0],data_in[31:0]};
//#####################################
//# CONFIG [0]
//#####################################
@ -107,13 +107,13 @@ module spi_slave_regs (/*AUTOARG*/
else if(spi_config_write)
spi_config[7:0] <= spi_wdata[7:0];
assign spi_en = ~spi_config[0]; // disable spi (for security)
assign irq_en = spi_config[1]; // enable interrupt
assign cpol = spi_config[2]; // cpol
assign cpha = spi_config[3]; // cpha
assign lsbfirst = spi_config[4]; // lsb shifted in first
assign valid = spi_config[5]; // user regs enable
assign emode = spi_config[6]; // epiphany mode
assign spi_en = hw_en & ~spi_config[0]; // disable spi (for security)
assign irq_en = spi_config[1]; // enable interrupt
assign cpol = spi_config[2]; // cpol
assign cpha = spi_config[3]; // cpha
assign lsbfirst = spi_config[4]; // lsb shifted in first
assign valid = spi_config[5]; // user regs enable
assign emode = spi_config[6]; // epiphany mode
//#####################################
//# STATUS [1]