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Adding platform agnostic dual ported memory and async fifo
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Andreas Olofsson
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@ -1,71 +1,113 @@
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/*
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Copyright (C) 2015 Adapteva, Inc.
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Contributed by Andreas Olofsson <andreas@adapteva.com>
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This program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program (see the file COPYING). If not, see
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<http://www.gnu.org/licenses/>.
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*/
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/*
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########################################################################
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Generic asynchronous FIFO
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Caution: There is no protection against overflow or underflow,
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driving logic should avoid wen on full or ren on empty.
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########################################################################
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*/
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module fifo_async(/*AUTOARG*/
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module fifo_async
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(/*AUTOARG*/
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// Outputs
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wr_full, wr_progfull, rd_data, rd_empty,
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rd_data, rd_fifo_empty, wr_fifo_full,
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// Inputs
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reset, wr_clk, wr_en, wr_data, rd_clk, rd_en
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reset, wr_clk, rd_clk, wr_write, wr_data, rd_read
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);
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parameter AW = 5; //fifo address width
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parameter DW = 16; //fifo data width
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//Reset
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input reset;
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parameter DW = 104;
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parameter AW = 2;
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//Write side interface
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input wr_clk; //write side clock
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input wr_en; //write enable
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input [DW-1:0] wr_data; //write data
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output wr_full; //fifo full
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output wr_progfull; //programmable full level
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//##########
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//# INPUTS
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//##########
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input reset;
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input wr_clk; //write clock
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input rd_clk; //read clock
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//Read side interface
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input rd_clk; //read side clock
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input rd_en; //read enable
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output [DW-1:0] rd_data; //read data
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output rd_empty; //fifo empty
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input wr_write;
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input [DW-1:0] wr_data;
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input rd_read;
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//###########
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//# OUTPUTS
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//###########
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output [DW-1:0] rd_data;
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output rd_fifo_empty;
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output wr_fifo_full;
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//Wires
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wire [DW/8-1:0] wr_en;
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wire [AW:0] wr_rd_gray_pointer;
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wire [AW:0] rd_wr_gray_pointer;
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wire [AW:0] wr_gray_pointer;
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wire [AW:0] rd_gray_pointer;
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wire [AW-1:0] rd_addr;
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wire [AW-1:0] wr_addr;
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assign wr_en[DW/8-1:0] = {(DW/8){wr_write}};
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memory_dp #(.DW(DW),.AW(AW)) memory_dp (
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// Outputs
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.rd_data (rd_data[DW-1:0]),
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// Inputs
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.wr_clk (wr_clk),
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.wr_en (wr_en[DW/8-1:0]),
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.wr_addr (wr_addr[AW-1:0]),
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.wr_data (wr_data[DW-1:0]),
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.rd_clk (rd_clk),
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.rd_en (1'b1),
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.rd_addr (rd_addr[AW-1:0]));
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//Read State Machine
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fifo_empty_block #(.AW(AW)) fifo_empty_block(
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// Outputs
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.rd_fifo_empty (rd_fifo_empty),
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.rd_addr (rd_addr[AW-1:0]),
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.rd_gray_pointer(rd_gray_pointer[AW:0]),
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// Inputs
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.reset (reset),
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.rd_clk (rd_clk),
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.rd_wr_gray_pointer(rd_wr_gray_pointer[AW:0]),
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.rd_read (rd_read));
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//Write State Machine
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fifo_full_block #(.AW(AW)) fifo_full_block(
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// Outputs
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.wr_fifo_full (wr_fifo_full),
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.wr_addr (wr_addr[AW-1:0]),
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.wr_gray_pointer (wr_gray_pointer[AW:0]),
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// Inputs
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.reset (reset),
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.wr_clk (wr_clk),
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.wr_rd_gray_pointer(wr_rd_gray_pointer[AW:0]),
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.wr_write (wr_write));
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//Dummy for now...
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assign rd_data = 103'b0;
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assign rd_empty = 1'b0;
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assign wr_full = 1'b0;
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assign wr_progfull = 1'b0;
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synchronizer #(.DW(AW+1)) rd2wr_sync (.out (wr_rd_gray_pointer[AW:0]),
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.in (rd_gray_pointer[AW:0]),
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.clk (wr_clk));
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//TODO:instatiate the right fifo
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//distributed RAM
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//32 x 103
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//async reset signal, assert high, full asserted on 16
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synchronizer #(.DW(AW+1)) wr2rd_sync (.out (rd_wr_gray_pointer[AW:0]),
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.in (wr_gray_pointer[AW:0]),
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.clk (rd_clk));
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endmodule // fifo_async
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// Local Variables:
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// verilog-library-directories:("." "../../common/hdl")
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// End:
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/*
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Copyright (C) 2013 Adapteva, Inc.
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Contributed by Andreas Olofsson, Roman Trogan <support@adapteva.com>
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This program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program (see the file COPYING). If not, see
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<http://www.gnu.org/licenses/>.
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*/
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@ -68,11 +68,8 @@ module fifo_async_emesh (/*AUTOARG*/
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assign emesh_data_out[31:0] = fifo_dout[71:40];
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assign emesh_srcaddr_out[31:0] = fifo_dout[103:72];
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//TODO: paraemtrize fifo properly
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fifo_async_104x32 fifo_async_104x32 (//outputs
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.dout (fifo_dout[103:0]),
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`ifdef TARGET_XILINX
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fifo_async_104x32 fifo_async_104x32 (.dout (fifo_dout[103:0]),
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.full (fifo_full),
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.empty (fifo_empty),
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.prog_full (fifo_progfull),
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@ -84,8 +81,25 @@ module fifo_async_emesh (/*AUTOARG*/
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.wr_en (emesh_access_in),
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.rd_en (fifo_read)
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);
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`elsif TARGET_CLEAN
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fifo_async #(.DW(104), .AW(5)) fifo_async (
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.rd_data (fifo_dout[103:0]),
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.wr_fifo_full (fifo_progfull),
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.rd_fifo_empty (fifo_empty),
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//inputs
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.reset (reset),
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.wr_clk (wr_clk),
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.rd_clk (rd_clk),
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.wr_data (fifo_din[103:0]),
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.wr_write (emesh_access_in),
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.rd_read (fifo_read)
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);
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`elsif TARGET_ALTERA
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//SOMETHING
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`endif
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endmodule // fifo_sync
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// Local Variables:
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// verilog-library-directories:("." "../../stubs/hdl")
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@ -1,25 +1,11 @@
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/*
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Copyright (C) 2014 Adapteva, Inc.
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Contributed by Andreas Olofsson <andreas@adapteva.com>
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This program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.This program is distributed in the hope
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that it will be useful,but WITHOUT ANY WARRANTY; without even the implied
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warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details. You should have received a copy
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of the GNU General Public License along with this program (see the file
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COPYING). If not, see <http://www.gnu.org/licenses/>.
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*/
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/*###########################################################################
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# Function: Dual port memory wrapper (one read/ one write port)
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#
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# To run without hardware platform dependancy, `define:
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# "TARGET_CLEAN"
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############################################################################
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*/
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`define USE_MEM_MODEL
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module memory_dp(/*AUTOARG*/
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// Outputs
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rd_data,
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@ -47,7 +33,9 @@ module memory_dp(/*AUTOARG*/
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//////////////////////
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//SIMPLE MEMORY MODEL
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//////////////////////
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`ifdef USE_MEM_MODEL
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`ifdef TARGET_CLEAN
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reg [DW-1:0] ram [MD-1:0];
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reg [DW-1:0] rd_data;
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@ -69,8 +57,7 @@ module memory_dp(/*AUTOARG*/
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endgenerate
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`elsif TARGET_XILINX
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//instantiate XILINX BRAM (based on parameter size)
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`elsif TARGET_ALTERA
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`endif
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@ -78,6 +65,20 @@ module memory_dp(/*AUTOARG*/
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endmodule // memory_dp
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/*
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Copyright (C) 2014 Adapteva, Inc.
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Contributed by Andreas Olofsson <andreas@adapteva.com>
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This program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.This program is distributed in the hope
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that it will be useful,but WITHOUT ANY WARRANTY; without even the implied
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warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details. You should have received a copy
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of the GNU General Public License along with this program (see the file
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COPYING). If not, see <http://www.gnu.org/licenses/>.
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*/
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