From 50c1845f3015a6b6f17c024d707d9418a0f7816a Mon Sep 17 00:00:00 2001
From: aolofsson <andreas@zeroasic.com>
Date: Mon, 26 Jul 2021 08:19:50 -0400
Subject: [PATCH] Adding synthesizable multipler

---
 common/hdl/oh_mult.v | 36 ++++++++++++++++++++++++++++++++++++
 1 file changed, 36 insertions(+)
 create mode 100644 common/hdl/oh_mult.v

diff --git a/common/hdl/oh_mult.v b/common/hdl/oh_mult.v
new file mode 100644
index 0000000..c7b7d96
--- /dev/null
+++ b/common/hdl/oh_mult.v
@@ -0,0 +1,36 @@
+//#############################################################################
+//# Function: Binary multiplier                                               #
+//#############################################################################
+//# Author:   Andreas Olofsson                                                #
+//# License:  MIT (see LICENSE file in OH! repository)                        #
+//#############################################################################
+
+module oh_mult
+  #(parameter DW   = 32,        // block width
+    parameter SYN  = "TRUE",    // synthesizable
+    parameter TYPE = "DEFAULT"  // implementation type
+    )
+   (
+    //Inputs
+    input [DW-1:0]    a,       // a input (multiplier)
+    input [DW-1:0]    b,       // b input (multiplicand)
+    input 	      asigned, // a operand is signed
+    input 	      bsigned, // b oeprand is signed
+    //Outputs
+    output [2*DW-1:0] product, // a*b final product
+    output [2*DW-1:0] sum,     // a*b partial sum
+    output [2*DW-1:0] carry    // a*b partial carry
+    );
+
+   generate
+      if(SYN=="TRUE")  begin
+	 wire a_sext = asigned & a[DW-1];
+	 wire b_sext = bsigned & b[DW-1];
+	 assign product[2*DW-1:0] = $signed({a_sext,a[DW-1:0]}) *
+				    $signed({b_sext,b[DW-1:0]});
+      end
+      else begin
+
+      end
+   endgenerate
+endmodule