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Fixing burst logic speed path

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- The burst signal was going fro lclk_div4 domain straight into the io high speed domain. There is quite a bit of logic on this signal. Instead of starting with false paths or multi cycle paths with firstedge, I changed the pipeline.
This commit is contained in:
Andreas Olofsson 2015-11-15 12:26:54 -05:00
parent f77938e9b0
commit 5197822f53
2 changed files with 6 additions and 7 deletions
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6
elink/hdl/etx_io.v
View File

@ -49,7 +49,6 @@ module etx_io (/*AUTOARG*/
reg [63:0] tx_double;
reg [2:0] tx_state;
reg tx_access_reg;
reg tx_burst_reg;
//############
//# WIRES
@ -99,7 +98,6 @@ module etx_io (/*AUTOARG*/
if(firstedge)
begin
tx_access_reg <= tx_access & ~tx_wait;
tx_burst_reg <= tx_burst & ~tx_wait;
end
//Pushback on wait
@ -136,8 +134,8 @@ module etx_io (/*AUTOARG*/
`CYCLE4 : tx_state[2:0] <= `CYCLE5;
`CYCLE5 : tx_state[2:0] <= `CYCLE6;
`CYCLE6 : tx_state[2:0] <= `CYCLE7;
`CYCLE7 : tx_state[2:0] <= tx_burst_reg & ~tx_wait ? `CYCLE4 :
`IDLE;
`CYCLE7 : tx_state[2:0] <= tx_burst & ~tx_wait ? `CYCLE4 :
`IDLE;
endcase // case (tx_state)
//#############################

7
elink/hdl/etx_protocol.v
View File

@ -43,7 +43,7 @@ module etx_protocol (/*AUTOARG*/
reg tx_access;
reg [PW-1:0] tx_packet;
reg tx_io_wait;
reg tx_burst;
wire etx_write;
wire [1:0] etx_datamode;
wire [3:0] etx_ctrlmode;
@ -78,7 +78,7 @@ module etx_protocol (/*AUTOARG*/
else if (tx_io_wait)
tx_io_wait <= 1'b0;
else
tx_io_wait <= etx_access & ~tx_burst;
tx_io_wait <= etx_access & ~tx_burst_in;
//Hold transaction while waiting
//This transaction should be flushed out on wait????
@ -92,6 +92,7 @@ module etx_protocol (/*AUTOARG*/
begin
tx_packet[PW-1:0] <= etx_packet[PW-1:0];
tx_access <= tx_enable & etx_access;
tx_burst <= tx_burst_in;
end
//#############################
@ -115,7 +116,7 @@ module etx_protocol (/*AUTOARG*/
==
{etx_ctrlmode[3:0],etx_datamode[1:0], etx_write};
assign tx_burst = tx_access & //avoid garbage
assign tx_burst_in = tx_access & //avoid garbage
~tx_wr_wait_reg & //clear on wait
etx_write & //write
(etx_datamode[1:0]==2'b11) & //double only