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Changed to 20 bit addressing for clarity in FPGA

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aolofsson 2014-11-05 19:49:18 -05:00
parent 2851e01228
commit 536613b230
2 changed files with 39 additions and 29 deletions
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25
ecfg/dv/dv_ecfg.v
View File

@ -5,7 +5,7 @@ module dv_ecfg();
reg clk;
reg reset;
reg mi_access;
reg [5:0] mi_addr;
reg [19:0] mi_addr;
reg [31:0] mi_data_in;
reg mi_write;
reg [1:0] test_state;
@ -19,7 +19,7 @@ module dv_ecfg();
reset = 1'b1; // reset is active
mi_write = 1'b0;
mi_access = 1'b0;
mi_addr[5:0] = 6'b0;
mi_addr[19:0] = 20'hf0340;
mi_data_in[31:0] = 32'h0;
test_state[1:0] = 2'b00;
#100
@ -42,29 +42,31 @@ module dv_ecfg();
2'b00:
if(~done)
begin
mi_addr[5:0] <= mi_addr[5:0]+1'b1;
mi_addr[19:0] <= mi_addr[19:0]+20'h4;
mi_data_in[5:0] <= mi_data_in[5:0]+1'b1;
end
else
begin
test_state <= 2'b01;
mi_addr[5:0] <= 6'b0;
mi_addr[19:0] <= 20'hf0340;
mi_write <= 1'b0;
end
2'b01:
if(~done)
begin
mi_addr[5:0] <= mi_addr[5:0]+1'b1;
mi_data_in[5:0] <= 32'hffffffff;
mi_addr[19:0] <= mi_addr[19:0]+20'h4;
mi_data_in[5:0] <= 32'hffffffff;
end
else
test_state <= 2'b01;
endcase// case (test_state[1:0])
wire done = (mi_addr[5:0]==6'b111111);
wire done = (mi_addr[19:0]==20'hf0360);
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [3:0] ecfg_cclk_div; // From ecfg of ecfg.v
wire ecfg_cclk_en; // From ecfg of ecfg.v
wire [3:0] ecfg_cclk_pllcfg; // From ecfg of ecfg.v
wire [11:0] ecfg_coreid; // From ecfg of ecfg.v
wire [11:0] ecfg_dataout; // From ecfg of ecfg.v
@ -72,6 +74,7 @@ module dv_ecfg();
wire ecfg_rx_gpio_mode; // From ecfg of ecfg.v
wire ecfg_rx_loopback_mode; // From ecfg of ecfg.v
wire ecfg_rx_mmu_mode; // From ecfg of ecfg.v
wire ecfg_sw_reset; // From ecfg of ecfg.v
wire [3:0] ecfg_tx_clkdiv; // From ecfg of ecfg.v
wire [3:0] ecfg_tx_ctrl_mode; // From ecfg of ecfg.v
wire ecfg_tx_enable; // From ecfg of ecfg.v
@ -85,6 +88,7 @@ module dv_ecfg();
/*AUTOINST*/
// Outputs
.mi_data_out (mi_data_out[31:0]),
.ecfg_sw_reset (ecfg_sw_reset),
.ecfg_tx_enable (ecfg_tx_enable),
.ecfg_tx_mmu_mode (ecfg_tx_mmu_mode),
.ecfg_tx_gpio_mode (ecfg_tx_gpio_mode),
@ -94,6 +98,7 @@ module dv_ecfg();
.ecfg_rx_mmu_mode (ecfg_rx_mmu_mode),
.ecfg_rx_gpio_mode (ecfg_rx_gpio_mode),
.ecfg_rx_loopback_mode (ecfg_rx_loopback_mode),
.ecfg_cclk_en (ecfg_cclk_en),
.ecfg_cclk_div (ecfg_cclk_div[3:0]),
.ecfg_cclk_pllcfg (ecfg_cclk_pllcfg[3:0]),
.ecfg_coreid (ecfg_coreid[11:0]),
@ -103,7 +108,7 @@ module dv_ecfg();
.reset (reset),
.mi_access (mi_access),
.mi_write (mi_write),
.mi_addr (mi_addr[5:0]),
.mi_addr (mi_addr[19:0]),
.mi_data_in (mi_data_in[31:0]));
@ -116,3 +121,7 @@ module dv_ecfg();
endmodule // dv_ecfg
// Local Variables:
// verilog-library-directories:("." "../hdl" "../../memory/hdl ")
// End:

43
ecfg/hdl/ecfg.v
View File

@ -86,15 +86,16 @@
########################################################################
*/
`define REG_ESYSRESET 6'h00
`define REG_ESYSCFGTX 6'h01
`define REG_ESYSCFGRX 6'h02
`define REG_ESYSCFGCLK 6'h03
`define REG_ESYSCOREID 6'h04
`define REG_ESYSVERSION 6'h05
`define REG_ESYSDATAIN 6'h06
`define REG_ESYSDATAOUT 6'h07
`define EVERSION 32'h01_02_03_04
`define E_REG_SYSRESET 20'hf0340
`define E_REG_SYSCFGTX 20'hf0344
`define E_REG_SYSCFGRX 20'hf0348
`define E_REG_SYSCFGCLK 20'hf034c
`define E_REG_SYSCOREID 20'hf0350
`define E_REG_SYSVERSION 20'hf0354
`define E_REG_SYSDATAIN 20'hf0358
`define E_REG_SYSDATAOUT 20'hf035c
`define E_VERSION 32'h01_02_03_04
module ecfg (/*AUTOARG*/
// Outputs
mi_data_out, ecfg_sw_reset, ecfg_tx_enable, ecfg_tx_mmu_mode,
@ -112,10 +113,10 @@ module ecfg (/*AUTOARG*/
COMPILE TIME PARAMETERS
######################################################################
*/
parameter EMAW = 12; //mmu table address width
parameter EMAW = 12; //mmu table address width
parameter EDW = 32; //Epiphany native data width
parameter EAW = 32; //Epiphany native address width
parameter IDW = 12; //Elink ID (row,column coordinate)
parameter IDW = 12; //Elink ID (row,column coordinate)
parameter RFAW = 5; //Number of registers=2^RFAW
@ -131,7 +132,7 @@ parameter RFAW = 5; //Number of registers=2^RFAW
input reset;
input mi_access;
input mi_write;
input [5:0] mi_addr;
input [19:0] mi_addr;
input [31:0] mi_data_in;
output [31:0] mi_data_out;
@ -211,14 +212,14 @@ parameter RFAW = 5; //Number of registers=2^RFAW
assign ecfg_read = mi_access & ~mi_write;
//address match signals
assign ecfg_reset_match = mi_addr[5:0]==`REG_ESYSRESET;
assign ecfg_cfgtx_match = mi_addr[5:0]==`REG_ESYSCFGTX;
assign ecfg_cfgrx_match = mi_addr[5:0]==`REG_ESYSCFGRX;
assign ecfg_cfgclk_match = mi_addr[5:0]==`REG_ESYSCFGCLK;
assign ecfg_coreid_match = mi_addr[5:0]==`REG_ESYSCOREID;
assign ecfg_version_match = mi_addr[5:0]==`REG_ESYSVERSION;
assign ecfg_datain_match = mi_addr[5:0]==`REG_ESYSDATAIN;
assign ecfg_dataout_match = mi_addr[5:0]==`REG_ESYSDATAOUT;
assign ecfg_reset_match = mi_addr[19:0]==`E_REG_SYSRESET;
assign ecfg_cfgtx_match = mi_addr[19:0]==`E_REG_SYSCFGTX;
assign ecfg_cfgrx_match = mi_addr[19:0]==`E_REG_SYSCFGRX;
assign ecfg_cfgclk_match = mi_addr[19:0]==`E_REG_SYSCFGCLK;
assign ecfg_coreid_match = mi_addr[19:0]==`E_REG_SYSCOREID;
assign ecfg_version_match = mi_addr[19:0]==`E_REG_SYSVERSION;
assign ecfg_datain_match = mi_addr[19:0]==`E_REG_SYSDATAIN;
assign ecfg_dataout_match = mi_addr[19:0]==`E_REG_SYSDATAOUT;
//Write enables
assign ecfg_reset_write = ecfg_reset_match & ecfg_write;
@ -287,7 +288,7 @@ parameter RFAW = 5; //Number of registers=2^RFAW
//###########################
//# ESYSVERSION
//###########################
assign ecfg_version_reg[31:0] = `EVERSION;
assign ecfg_version_reg[31:0] = `E_VERSION;
//###########################
//# ESYSDATAIN