FPGA/oh
1
0
Fork 0
mirror of https://github.com/aolofsson/oh.git synced 2025-01-17 20:02:53 +08:00
Code Issues Projects Releases Wiki Activity

Added test/dv for gpio block

Browse Source 
-note: with the number of blocks growing, there really needs to be more common iinfrastructure around the builds
-every block should be independent, yet you don't want to repeat the scripts
This commit is contained in:
Andreas Olofsson 2016-03-05 16:10:06 -05:00
parent 16ddde2e39
commit 53838f35ea
4 changed files with 26 additions and 16 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
gpio/dv/build.sh
View File

@ -2,7 +2,8 @@
DV="../../common/dv/dv_top.v" DV="../../common/dv/dv_top.v"
DUT="dut_gpio.v" DUT="dut_gpio.v"
iverilog -g2005 -DTARGET_SIM=1 \ ROOT="gpio"
iverilog -o $ROOT.bin -g2005 -DTARGET_SIM=1 \
$DV \ $DV \
$DUT \ $DUT \
-y ../hdl \ -y ../hdl \

22
gpio/dv/dut_gpio.v
View File

@ -2,7 +2,7 @@ module dut(/*AUTOARG*/
// Outputs // Outputs
dut_active, clkout, wait_out, access_out, packet_out, dut_active, clkout, wait_out, access_out, packet_out,
// Inputs // Inputs
clk, clk1, clk2, nreset, vdd, vss, access_in, packet_in, wait_in clk1, clk2, nreset, vdd, vss, access_in, packet_in, wait_in
); );
parameter AW = 32; parameter AW = 32;
@ -40,9 +40,6 @@ module dut(/*AUTOARG*/
input [N-1:0] wait_in; input [N-1:0] wait_in;
/*AUTOINPUT*/ /*AUTOINPUT*/
// Beginning of automatic inputs (from unused autoinst inputs)
input clk; // To gpio of gpio.v
// End of automatics
/*AUTOWIRE*/ /*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs) // Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [AW-1:0] gpio_data; // From gpio of gpio.v wire [AW-1:0] gpio_data; // From gpio of gpio.v
@ -52,6 +49,7 @@ module dut(/*AUTOARG*/
wire [31:0] reg_rdata; // From gpio of gpio.v wire [31:0] reg_rdata; // From gpio of gpio.v
// End of automatics // End of automatics
wire clk;
wire [AW-1:0] gpio_in; // To gpio of gpio.v wire [AW-1:0] gpio_in; // To gpio of gpio.v
reg [N-1:0] access_out; reg [N-1:0] access_out;
@ -59,7 +57,6 @@ module dut(/*AUTOARG*/
//DUT //DUT
//###################################################################### //######################################################################
assign gpio_in[AW-1:0] = 32'h87654321;
assign wait_out[N-1:0] = 'b0; assign wait_out[N-1:0] = 'b0;
assign dut_active = 1'b1; assign dut_active = 1'b1;
assign clkout = clk1; assign clkout = clk1;
@ -79,24 +76,27 @@ module dut(/*AUTOARG*/
.srcaddr_out ({(AW){1'b0}}) .srcaddr_out ({(AW){1'b0}})
); );
/*gpio AUTO_TEMPLATE(.gpio_irq (gpio_irq), /*gpio AUTO_TEMPLATE(
.gpio_irq (gpio_irq),
.gpio_\(.*\) (gpio_\1[AW-1:0]), .gpio_\(.*\) (gpio_\1[AW-1:0]),
.reg_rdata (reg_rdata[31:0]),
.reg_\(.*\) (\1_in[]),
); );
*/ */
gpio #(.N(AW)) gpio #(.N(AW))
gpio (.reg_access (access_in[0]), gpio (.gpio_in (gpio_out[AW-1:0]),
.reg_packet (packet_in[PW-1:0]),
.gpio_in (gpio_in[AW-1:0]),
/*AUTOINST*/ /*AUTOINST*/
// Outputs // Outputs
.reg_rdata (reg_rdata[31:0]), .reg_rdata (reg_rdata[31:0]), // Templated
.gpio_out (gpio_out[AW-1:0]), // Templated .gpio_out (gpio_out[AW-1:0]), // Templated
.gpio_oen (gpio_oen[AW-1:0]), // Templated .gpio_oen (gpio_oen[AW-1:0]), // Templated
.gpio_irq (gpio_irq), // Templated .gpio_irq (gpio_irq), // Templated
.gpio_data (gpio_data[AW-1:0]), // Templated .gpio_data (gpio_data[AW-1:0]), // Templated
// Inputs // Inputs
.nreset (nreset), .nreset (nreset),
.clk (clk)); .clk (clk),
.reg_access (access_in), // Templated
.reg_packet (packet_in[PW-1:0])); // Templated
endmodule // dut endmodule // dut

2
gpio/dv/run.sh
View File

@ -4,4 +4,4 @@ then
rm test_0.emf rm test_0.emf
fi fi
cp $1 test_0.emf cp $1 test_0.emf
./gpio.vvp ./gpio.bin

15
gpio/dv/tests/test_regs.emf
View File

@ -1,5 +1,14 @@
DEADBEEF_76543210_00000000_05_0010 //write odata DEADBEEF_99999999_00000000_05_0010 //write gpio_oen
DEADBEEF_fedcba98_00000010_05_0010 //write oen DEADBEEF_FFFFFFFF_00000008_05_0010 //write gpio_out
DEADBEEF_DEADBEEF_00000010_04_0010 //read oen DEADBEEF_BBBBBBBB_00000010_05_0010 //write gpio_ien
DEADBEEF_CCCCCCCC_00000018_05_0010 //write gpio_in
DEADBEEF_11111111_00000020_05_0010 //write gpio_outand
DEADBEEF_22222222_00000028_05_0010 //write gpio_outorr
DEADBEEF_FFFFFFFF_00000030_05_0010 //write gpio_outxor
DEADBEEF_55555555_00000038_05_0010 //write gpio_irqmask