diff --git a/emmu/hdl/emmu.v b/emmu/hdl/emmu.v
index f6f53dd..9255789 100644
--- a/emmu/hdl/emmu.v
+++ b/emmu/hdl/emmu.v
@@ -19,8 +19,8 @@ module emmu (/*AUTOARG*/
    // Outputs
    mi_dout, emesh_access_out, emesh_packet_out, emesh_packet_hi_out,
    // Inputs
-   reset, clk, mmu_en, mmu_bp, mi_en, mi_we, mi_addr, mi_din,
-   emesh_access_in, emesh_packet_in, emesh_wait_in
+   reset, rd_clk, wr_clk, mmu_en, mmu_bp, mi_en, mi_we, mi_addr,
+   mi_din, emesh_access_in, emesh_packet_in, emesh_wait_in
    );
    parameter DW     = 32;         //data width
    parameter AW     = 32;         //address width 
@@ -34,7 +34,8 @@ module emmu (/*AUTOARG*/
    /*DATAPATH CLOCk             */
    /*****************************/  
    input 	     reset;
-   input 	     clk; 
+   input 	     rd_clk;
+   input 	     wr_clk;
 
    /*****************************/
    /*MMU LOOKUP DATA            */
@@ -92,6 +93,9 @@ module emmu (/*AUTOARG*/
    //write data
    assign mi_wr_data[63:0] = {mi_din[31:0], mi_din[31:0]};
 
+   //todo: implement readback? worth it?
+   assign mi_dout[DW-1:0] = 'b0;
+
    /*****************************/
    /*MMU READ  LOGIC            */
    /*****************************/
@@ -103,11 +107,11 @@ module emmu (/*AUTOARG*/
 					   // Outputs
 					   .rd_data		(emmu_lookup_data[MW-1:0]),
 					   // Inputs
-					   .wr_clk		(clk),
+					   .wr_clk		(wr_clk),
 					   .wr_en		(mi_wr_vec[5:0]),
 					   .wr_addr		(mi_addr[14:3]),
 					   .wr_data		(mi_wr_data[MW-1:0]),
-					   .rd_clk		(clk),
+					   .rd_clk		(rd_clk),
 					   .rd_en		(emesh_access_in),
 					   .rd_addr		(emmu_rd_addr[MAW-1:0])
 					   );
@@ -118,13 +122,13 @@ module emmu (/*AUTOARG*/
    //pipeline to compensate for table lookup pipeline 
    //assumes one cycle memory access!     
   
-   always @ (posedge  clk or posedge reset)
+   always @ (posedge  rd_clk or posedge reset)
      if(reset)
        emesh_access_out <= 1'b0;
      else if(~emesh_wait_in)
        emesh_access_out         <= emesh_access_in;
    
-   always @ (posedge clk)
+   always @ (posedge rd_clk)
      if(emesh_access_in & ~emesh_wait_in)   
        emesh_packet_reg[PW-1:0]  <= emesh_packet_in[PW-1:0];