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Apply CFG_ASIC at the top level

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Commit 381ba09 adds CFG_ASIC as a primary variable.  This commit
allows this to be set in the system_build.tcl script at build time


Signed-off-by: Peter Saunderson <peteasa@gmail.com>
This commit is contained in:
Peter Saunderson 2016-08-17 14:22:04 +01:00
parent aac3d5b3a2
commit 55118cee9d
3 changed files with 18 additions and 0 deletions
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8
src/common/fpga/system_build.tcl
View File

@ -11,6 +11,14 @@ make_wrapper -files [get_files $projdir/${design}.srcs/sources_1/bd/system/syste
remove_files -fileset sources_1 $projdir/${design}.srcs/sources_1/bd/system/hdl/system_wrapper.v
add_files -fileset sources_1 -norecurse $projdir/${design}.srcs/sources_1/bd/system/hdl/system_wrapper.v
###########################################################
# PREPARE FOR SYNTHESIS
###########################################################
if {[info exists oh_synthesis_options]} {
puts "INFO: Synthesis with following options: $oh_synthesis_options"
set_property -name {STEPS.SYNTH_DESIGN.ARGS.MORE OPTIONS} -value $oh_synthesis_options -objects [get_runs synth_1]
}
###########################################################
# SYNTHESIS
###########################################################

5
src/parallella/fpga/headless_e16_z7010/system_params.tcl
View File

@ -20,3 +20,8 @@ set constraints_files [list \
../parallella_timing.xdc \
../parallella_io.xdc \
]
###########################################################
# PREPARE FOR SYNTHESIS
###########################################################
set oh_synthesis_options "-verilog_define CFG_ASIC=0"

5
src/parallella/fpga/headless_e16_z7020/system_params.tcl
View File

@ -21,3 +21,8 @@ set constraints_files [list \
../parallella_io.xdc \
../parallella_7020_io.xdc \
]
###########################################################
# PREPARE FOR SYNTHESIS
###########################################################
set oh_synthesis_options "-verilog_define CFG_ASIC=0"