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Synthesis: parameter = `CFG_ASIC not accepted in module declaration

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Vivado does not pre-process defines in the module declaration.
The result is that each module with this type of declaration is AutoDisabled by Vivado

Moving the top level define to a localparam fixes this problem

Signed-off-by: Peter Saunderson <peteasa@gmail.com>
This commit is contained in:
Peter Saunderson 2016-08-17 15:06:01 +01:00
parent 55118cee9d
commit 553ee31400
20 changed files with 57 additions and 51 deletions
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5
src/common/hdl/oh_clockgate.v
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@ -5,14 +5,15 @@
//# License: MIT (see LICENSE file in OH! repository) #
//#############################################################################
module oh_clockgate # (parameter ASIC = `CFG_ASIC)
(
module oh_clockgate (
input clk, // clock input
input te, // test enable enable
input en, // enable (from positive edge FF)
output eclk // enabled clock output
);
localparam ASIC = `CFG_ASIC; // use ASIC lib
generate
if(ASIC)
begin : asic

7
src/common/hdl/oh_clockmux.v
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@ -5,8 +5,7 @@
//# License: MIT (see LICENSE file in OH! repository) #
//#############################################################################
module oh_clockmux #(parameter ASIC = `CFG_ASIC, // use ASIC lib
parameter N = 1) // number of clock inputs
module oh_clockmux #(parameter N = 1) // number of clock inputs
(
input clk, // local clock to sync enable to
input [N-1:0] en, // one hot enable vector
@ -14,7 +13,9 @@ module oh_clockmux #(parameter ASIC = `CFG_ASIC, // use ASIC lib
output clkout
);
generate
localparam ASIC = `CFG_ASIC;
generate
if(ASIC)
begin : g0
asic_clockmux #(.N(N)) asic_clockmux (.clk(clk),

5
src/common/hdl/oh_clockor.v
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@ -5,13 +5,14 @@
//# License: MIT (see LICENSE file in OH! repository) #
//#############################################################################
module oh_clockor #(parameter ASIC = `CFG_ASIC, // use ASIC lib
parameter N = 1) // number of clock inputs
module oh_clockor #(parameter N = 1) // number of clock inputs
(
input [N-1:0] clkin,// one hot clock inputs (only one is active!)
output clkout
);
localparam ASIC = `CFG_ASIC;
generate
if(ASIC)
begin : asic

5
src/common/hdl/oh_csa32.v
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@ -5,8 +5,7 @@
//# License: MIT (see LICENSE file in OH! repository) #
//#############################################################################
module oh_csa32 #(parameter DW = 1, // data width
parameter ASIC = 0 // use asic library
module oh_csa32 #(parameter DW = 1 // data width
)
( input [DW-1:0] in0, //input
input [DW-1:0] in1,//input
@ -15,6 +14,8 @@ module oh_csa32 #(parameter DW = 1, // data width
output [DW-1:0] c //carry
);
localparam ASIC = `CFG_ASIC; // use asic library
generate
if(ASIC)
begin : asic

5
src/common/hdl/oh_csa42.v
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@ -5,8 +5,7 @@
//# License: MIT (see LICENSE file in OH! repository) #
//#############################################################################
module oh_csa42 #( parameter DW = 1 , // data width
parameter ASIC = 0 // use asic library
module oh_csa42 #( parameter DW = 1 // data width
)
( input [DW-1:0] in0, //input
input [DW-1:0] in1,//input
@ -18,6 +17,8 @@ module oh_csa42 #( parameter DW = 1 , // data width
output [DW-1:0] cout //carry out
);
localparam ASIC = `CFG_ASIC; // use asic library
generate
if(ASIC)
begin

3
src/common/hdl/oh_delay.v
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@ -6,13 +6,14 @@
//#############################################################################
module oh_delay #(parameter DW = 1, // width of data
parameter ASIC = 0, // use asic library
parameter DELAY= 0 // delay
)
(
input [DW-1:0] in, // input
output [DW-1:0] out // output
);
localparam ASIC = `CFG_ASIC; // use asic library
generate
if(ASIC)

5
src/common/hdl/oh_dsync.v
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@ -6,8 +6,7 @@
//#############################################################################
module oh_dsync #(parameter PS = 2, // number of sync stages
parameter DELAY = 0, // random delay
parameter ASIC = `CFG_ASIC // use asic library
parameter DELAY = 0 // random delay
)
(
input clk, // clock
@ -16,6 +15,8 @@ module oh_dsync #(parameter PS = 2, // number of sync stages
output dout // synchronized data
);
localparam ASIC = `CFG_ASIC; // use asic library
generate
if(ASIC)
begin : g0

8
src/common/hdl/oh_fifo_generic.v
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@ -27,8 +27,6 @@ module oh_fifo_generic #(parameter DW = 104, // FIFO width
output [AW-1:0] rd_count, // NOT IMPLEMENTED
output [AW-1:0] wr_count // NOT IMPLEMENTED
);
localparam ASIC = `CFG_ASIC;
//regs
reg [AW:0] wr_addr; // extra bit for wraparound comparison
@ -67,13 +65,11 @@ module oh_fifo_generic #(parameter DW = 104, // FIFO width
//# Reset synchronizers
//###########################
oh_rsync #(.ASIC(ASIC))
wr_rsync (.nrst_out (wr_nreset),
oh_rsync wr_rsync (.nrst_out (wr_nreset),
.clk (wr_clk),
.nrst_in (nreset));
oh_rsync #(.ASIC(ASIC))
rd_rsync (.nrst_out (rd_nreset),
oh_rsync rd_rsync (.nrst_out (rd_nreset),
.clk (rd_clk),
.nrst_in (nreset));

5
src/common/hdl/oh_lat0.v
View File

@ -5,13 +5,14 @@
//# License: MIT (see LICENSE file in OH! repository) #
//#############################################################################
module oh_lat0 #(parameter DW = 1, // data width
parameter ASIC = `CFG_ASIC // use ASIC lib
module oh_lat0 #(parameter DW = 1 // data width
)
( input clk, // clk, latch when clk=0
input [DW-1:0] in, // input data
output [DW-1:0] out // output data (stable/latched when clk=1)
);
localparam ASIC = `CFG_ASIC; // use ASIC lib
generate
if(ASIC)

5
src/common/hdl/oh_lat1.v
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@ -5,14 +5,15 @@
//# License: MIT (see LICENSE file in OH! repository) #
//#############################################################################
module oh_lat1 #(parameter DW = 1, //data width
parameter ASIC = `CFG_ASIC // use ASIC lib
module oh_lat1 #(parameter DW = 1 //data width
)
( input clk, // clk, latch when clk=1
input [DW-1:0] in, // input data
output [DW-1:0] out // output data (stable/latched when clk=0)
);
localparam ASIC = `CFG_ASIC; // use ASIC lib
generate
if(ASIC)
begin : g0

3
src/common/hdl/oh_memory_dp.v
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@ -8,7 +8,6 @@
module oh_memory_dp # (parameter DW = 104, //memory width
parameter DEPTH = 32, //memory depth
parameter PROJ = "", //project name
parameter ASIC = 0, // use ASIC lib
parameter MCW = 8, //repair/config vector width
parameter AW = $clog2(DEPTH) // address bus width
)
@ -33,6 +32,8 @@ module oh_memory_dp # (parameter DW = 104, //memory width
input [AW-1:0] bist_addr, // address
input [DW-1:0] bist_din // data input
);
localparam ASIC = `CFG_ASIC; // use asic library
generate
if(ASIC)

5
src/common/hdl/oh_memory_sp.v
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@ -7,7 +7,6 @@
module oh_memory_sp # (parameter DW = 104, // memory width
parameter DEPTH = 32, // memory depth
parameter ASIC = `CFG_ASIC, // use ASIC lib
parameter MCW = 8, // repair/config width
parameter AW = $clog2(DEPTH) // address bus width
)
@ -34,8 +33,8 @@ module oh_memory_sp # (parameter DW = 104, // memory width
input [DW-1:0] bist_din // data input
);
localparam ASIC = `CFG_ASIC; // use ASIC lib
generate
if(ASIC)
begin : g0

8
src/common/hdl/oh_pwr_gate.v
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@ -5,14 +5,14 @@
//# License: MIT (see LICENSE file in OH! repository) #
//#############################################################################
module oh_pwr_gate #(parameter ASIC = 0 // use ASIC lib
)
(input npower, // active low power on
module oh_pwr_gate (
input npower, // active low power on
input vdd, // input supply
output vddg // gated output supply
);
localparam ASIC = `CFG_ASIC; // use asic library
`ifdef TARGET_SIM
assign vddg = ((vdd===1'b1) && (npower===1'b0)) ? 1'b1 : 1'bX;
`else

5
src/common/hdl/oh_pwr_isohi.v
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@ -5,8 +5,7 @@
//# License: MIT (see LICENSE file in OH! repository) #
//#############################################################################
module oh_pwr_isohi #(parameter DW = 1, // width of data inputs
parameter ASIC = `CFG_ASIC // use ASIC lib
module oh_pwr_isohi #(parameter DW = 1 // width of data inputs
)
(
input iso,// active low isolation signal
@ -14,6 +13,8 @@ module oh_pwr_isohi #(parameter DW = 1, // width of data inputs
output [DW-1:0] out // out = iso | in
);
localparam ASIC = `CFG_ASIC; // use ASIC lib
generate
if(ASIC)
begin : asic

5
src/common/hdl/oh_pwr_isolo.v
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@ -5,14 +5,15 @@
//# License: MIT (see LICENSE file in OH! repository) #
//#############################################################################
module oh_pwr_isolo #(parameter DW = 1, // width of data inputs
parameter ASIC = `CFG_ASIC // use ASIC lib
module oh_pwr_isolo #(parameter DW = 1 // width of data inputs
)
(
input iso,// active low isolation signal
input [DW-1:0] in, // input signal
output [DW-1:0] out // out = ~iso & in
);
localparam ASIC = `CFG_ASIC; // use ASIC lib
generate
if(ASIC)

7
src/common/hdl/oh_reg0.v
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@ -5,15 +5,16 @@
//# License: MIT (see LICENSE file in OH! repository) #
//#############################################################################
module ohr_reg0 #(parameter DW = 1, // data width
parameter ASIC = `CFG_ASIC // use ASIC lib
module ohr_reg0 #(parameter DW = 1 // data width
)
( input nreset, //async active low reset
input clk, // clk, latch when clk=0
input [DW-1:0] in, // input data
output [DW-1:0] out // output data (stable/latched when clk=1)
);
localparam ASIC = `CFG_ASIC; // use ASIC lib
generate
if(ASIC)
begin : g0

5
src/common/hdl/oh_reg1.v
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@ -5,14 +5,15 @@
//# License: MIT (see LICENSE file in OH! repository) #
//#############################################################################
module oh_reg1 #(parameter DW = 1, // data width
parameter ASIC = `CFG_ASIC // use ASIC lib
module oh_reg1 #(parameter DW = 1 // data width
)
( input nreset, //async active low reset
input clk, // clk, latch when clk=0
input [DW-1:0] in, // input data
output [DW-1:0] out // output data (stable/latched when clk=1)
);
localparam ASIC = `CFG_ASIC;
generate
if(ASIC)

6
src/common/hdl/oh_rsync.v
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@ -5,14 +5,16 @@
//# License: MIT (see LICENSE file in OH! repository) #
//#############################################################################
module oh_rsync #(parameter PS = 2, // number of sync stages
parameter ASIC = `CFG_ASIC // use asic library
module oh_rsync #(parameter PS = 2 // number of sync stages
)
(
input clk,
input nrst_in,
output nrst_out
);
localparam ASIC = `CFG_ASIC; // use ASIC lib
generate
if(ASIC)
begin : g0

6
src/common/hdl/oh_standby.v
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@ -6,7 +6,6 @@
//#############################################################################
module oh_standby #( parameter PD = 5, // cycles to stay awake after "wakeup"
parameter ASIC = `CFG_ASIC, // use ASIC lib
parameter N = 5) // project name
(
input clkin, //clock input
@ -15,7 +14,7 @@ module oh_standby #( parameter PD = 5, // cycles to stay awake after "wakeup"
input idle, //core is in idle
output clkout //clock output
);
//Wire declarations
reg [PD-1:0] wakeup_pipe;
reg idle_reg;
@ -43,8 +42,7 @@ module oh_standby #( parameter PD = 5, // cycles to stay awake after "wakeup"
~idle; //core not in idle
// Clock gating cell
oh_clockgate #(.ASIC(ASIC))
oh_clockgate (.eclk(clkout),
oh_clockgate oh_clockgate (.eclk(clkout),
.clk(clkin),
.en(clk_en),
.te(1'b0));

5
src/mio/hdl/mtx_io.v
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@ -34,8 +34,6 @@ module mtx_io (/*AUTOARG*/
//#####################################################################
//# BODYINTER
//#####################################################################
localparam ASIC = `CFG_ASIC;
//Regs
reg tx_access;
@ -51,8 +49,7 @@ module mtx_io (/*AUTOARG*/
//########################################
//synchronize reset to io_clk
oh_rsync #(.ASIC(ASIC))
oh_rsync(.nrst_out (io_nreset),
oh_rsync oh_rsync(.nrst_out (io_nreset),
.clk (io_clk),
.nrst_in (nreset));