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Baking in the IO wait signal into rd/wr wait
-Separate waits for rd/wr wait -Adding wait to protocol block as well -io_wait always goes through -using active frame signal to select/clear data for output
This commit is contained in:
Andreas Olofsson
parent
dcf72537e4
commit
570fbffd7f
@ -1,7 +1,6 @@
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module etx_protocol (/*AUTOARG*/
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// Outputs
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etx_rd_wait, etx_wr_wait, etx_wait, etx_io_wait, tx_frame_par,
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tx_data_par,
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etx_rd_wait, etx_wr_wait, tx_frame_par, tx_data_par,
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// Inputs
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reset, clk, testmode, etx_access, etx_packet, tx_enable, tp_enable,
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gpio_enable, gpio_data, chipid, tx_rd_wait, tx_wr_wait
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@ -26,8 +25,6 @@ module etx_protocol (/*AUTOARG*/
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//Pushback signals
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output etx_rd_wait;
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output etx_wr_wait;
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output etx_wait; //for pipeline
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output etx_io_wait; //for arbiter
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//Enble transmit
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input tx_enable; //transmit enable
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@ -45,11 +42,10 @@ module etx_protocol (/*AUTOARG*/
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//###################################################################
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//# Local regs & wires
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//###################################################################
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reg etx_sample; //hold for second cycle
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reg [7:0] tx_frame_par;
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reg [127:0] tx_data_reg; //sample transaction on one clock cycle
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reg rd_wait_sync;
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reg wr_wait_sync;
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reg [127:0] tx_data_reg;
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wire tx_rd_wait_sync;
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wire tx_wr_wait_sync;
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wire etx_write;
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wire [1:0] etx_datamode;
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@ -59,6 +55,8 @@ module etx_protocol (/*AUTOARG*/
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wire [AW-1:0] etx_srcaddr;
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wire [PW-1:0] etx_packet_mux;
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reg [PW-1:0] testpacket;
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wire etx_valid;
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reg etx_io_wait;
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//Testmode logic
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always @( posedge clk or posedge reset )
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@ -97,22 +95,32 @@ module etx_protocol (/*AUTOARG*/
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);
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//Transmit packet enable
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assign etx_enable = (testmode | tx_enable) & ~(etx_dstaddr[31:20]==ID) ;
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//Only set valid if not wait
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assign etx_valid = testmode |
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(tx_enable & etx_access & ~(etx_dstaddr[31:20]==ID)) &
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((etx_write & ~tx_wr_wait_sync) |
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(~etx_write & ~tx_rd_wait_sync)
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);
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//One cycle hold for every transaction
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always @( posedge clk or posedge reset )
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if(reset)
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etx_io_wait <= 1'b0;
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else
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etx_io_wait <= etx_valid & ~etx_io_wait;
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// TODO: Bursts
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always @( posedge clk or posedge reset )
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begin
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if(reset)
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begin
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etx_sample <= 1'b1;
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tx_frame_par[7:0] <= 8'd0;
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tx_frame_par[7:0] <= 8'd0;
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tx_data_reg[127:0] <= 'd0;
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end
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else
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begin
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if( etx_enable & etx_access & etx_sample ) //first cycle
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if( etx_valid & ~etx_io_wait ) //first cycle
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begin
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etx_sample <= 1'b0;
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tx_frame_par[7:0] <= 8'h3F;
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tx_data_reg[127:0] <= {etx_data[31:0],
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etx_srcaddr[31:0],
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@ -124,31 +132,28 @@ module etx_protocol (/*AUTOARG*/
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etx_dstaddr[3:0], etx_datamode[1:0], etx_write, etx_access // B5
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};
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end
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else if(etx_enable & ~etx_sample ) //second cycle (1)
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else if(etx_io_wait ) //second cycle (1), completes transaction
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begin
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etx_sample <= 1'b1;
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tx_frame_par[7:0] <= 8'hFF;
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end
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else
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begin
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etx_sample <= 1'b1;
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tx_frame_par[7:0] <= 'd0;
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tx_data_reg[127:0] <= 'd0;
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tx_frame_par[7:0] <= 'd0;
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tx_data_reg[127:0] <= 'd0;
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end
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end // else: !if(reset)
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end // always @ ( posedge txlclk_p or posedge reset )
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//After first sample, etx_sample-->0 use as indicator to sample in data.
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assign tx_data_par[63:0] = ~etx_sample ? tx_data_reg[63:0] : //first cycle
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tx_data_reg[127:64];//all others, 0 or upper
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assign tx_data_par[63:0] = (tx_frame_par[0] & etx_io_wait) ? tx_data_reg[63:0] :
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(tx_frame_par[0] & ~etx_io_wait) ? tx_data_reg[127:64] :
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64'b0;
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//#############################
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//# Wait signals (async)
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//#############################
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synchronizer #(.DW(1)) rd_sync (// Outputs
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.out (etx_rd_wait),
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.out (tx_rd_wait_sync),
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// Inputs
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.in (tx_rd_wait),
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.clk (clk),
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@ -156,24 +161,17 @@ module etx_protocol (/*AUTOARG*/
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);
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synchronizer #(.DW(1)) wr_sync (// Outputs
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.out (etx_wr_wait),
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.out (tx_wr_wait_sync),
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// Inputs
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.in (tx_wr_wait),
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.clk (clk),
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.reset (reset)
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);
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//#############################
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//# Pipeline stall
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//#############################
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assign etx_io_wait = ~etx_sample;
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assign etx_wait = etx_io_wait |
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etx_rd_wait |
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etx_wr_wait;
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//Stall for all etx pipeline
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assign etx_wr_wait = tx_wr_wait_sync | etx_io_wait;
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assign etx_rd_wait = tx_rd_wait_sync | etx_io_wait;
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endmodule // etx_protocol
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// Local Variables:
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// verilog-library-directories:("." "../../common/hdl")
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@ -185,7 +183,8 @@ endmodule // etx_protocol
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This file is part of the Parallella Project.
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Copyright (C) 2014 Adapteva, Inc.
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Contributed by Fred Huettig <fred@adapteva.com>
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Contributed by Fred Huettig <fred@adapteva.com>
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Contributed by Andreas Olofsson <andreas@adapteva.com>
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This program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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