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Updating broken fifo (wip)

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aolofsson 2022-10-05 08:36:41 -04:00
parent 69a0dd2d3d
commit 5744252f91
2 changed files with 33 additions and 65 deletions
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63
stdlib/rtl/oh_fifo_async.v
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@ -18,9 +18,9 @@ module oh_fifo_async
parameter PROGFULL = DEPTH-1, // programmable almost full level parameter PROGFULL = DEPTH-1, // programmable almost full level
parameter SHAPE = "SQUARE" // hard macro shape (square, tall, wide) parameter SHAPE = "SQUARE" // hard macro shape (square, tall, wide)
) )
(//nreset (// nreset
input nreset, input nreset,
//write port // write port
input wr_clk, input wr_clk,
input [N-1:0] wr_din, // data to write input [N-1:0] wr_din, // data to write
input wr_en, // write fifo input wr_en, // write fifo
@ -28,26 +28,12 @@ module oh_fifo_async
output wr_almost_full, //one entry left output wr_almost_full, //one entry left
output wr_prog_full, //programmable full level output wr_prog_full, //programmable full level
output [AW-1:0] wr_count, // pessimistic report of entries from wr side output [AW-1:0] wr_count, // pessimistic report of entries from wr side
//read port // read port
input rd_clk, input rd_clk,
output [N-1:0] rd_dout, // output data (next cycle) output [N-1:0] rd_dout, // output data (next cycle)
input rd_en, // read fifo input rd_en, // read fifo
output rd_empty, // fifo is empty output rd_empty, // fifo is empty
output [AW-1:0] rd_count, // pessimistic report of entries from rd side output [AW-1:0] rd_count // pessimistic report of entries from rd side
// BIST interface
input bist_en, // bist enable
input bist_we, // write enable global signal
input [N-1:0] bist_wem, // write enable vector
input [AW-1:0] bist_addr, // address
input [N-1:0] bist_din, // data input
input [N-1:0] bist_dout, // data input
// Power/repair (hard macro only)
input shutdown, // shutdown signal
input vss, // ground signal
input vdd, // memory array power
input vddio, // periphery/io power
input [7:0] memconfig, // generic memory config
input [7:0] memrepair // repair vector
); );
//local wires //local wires
@ -57,7 +43,6 @@ module oh_fifo_async
wire [AW:0] wr_addr_gray_sync; wire [AW:0] wr_addr_gray_sync;
wire [AW:0] rd_addr_gray; wire [AW:0] rd_addr_gray;
wire [AW:0] rd_addr_gray_sync; wire [AW:0] rd_addr_gray_sync;
wire [AW:0] rd_addr_sync;
wire fifo_write; wire fifo_write;
wire rd_nreset; wire rd_nreset;
wire wr_nreset; wire wr_nreset;
@ -100,14 +85,10 @@ module oh_fifo_async
else if(rd_en) else if(rd_en)
rd_addr[AW:0] <= rd_addr[AW:0] + 'd1; rd_addr[AW:0] <= rd_addr[AW:0] + 'd1;
//############################################ //###########################
//# Synchronizaztion logic for async FIFO //# WRITE --> READ SYNC
//############################################ //###########################
//###########################
//# WRITE --> READ
//###########################
// convert to gray code (only one bit can toggle)
oh_bin2gray #(.N(AW+1)) oh_bin2gray #(.N(AW+1))
wr_bin2gray (.out (wr_addr_gray[AW:0]), wr_bin2gray (.out (wr_addr_gray[AW:0]),
.in (wr_addr[AW:0])); .in (wr_addr[AW:0]));
@ -121,7 +102,7 @@ module oh_fifo_async
.din (wr_addr_gray[AW:0])); .din (wr_addr_gray[AW:0]));
//########################### //###########################
//# READ ---> WRITE //# READ ---> WRITE SYNC
//########################### //###########################
oh_bin2gray #(.N(AW+1)) oh_bin2gray #(.N(AW+1))
@ -144,8 +125,8 @@ module oh_fifo_async
assign rd_empty = (rd_addr_gray[AW:0] == wr_addr_gray_sync[AW:0]); assign rd_empty = (rd_addr_gray[AW:0] == wr_addr_gray_sync[AW:0]);
// fifo full // fifo full
assign wr_full = (wr_addr[AW-1:0] == rd_addr_sync[AW-1:0]) & assign wr_full = (wr_addr_gray[AW-1:0] == rd_addr_gray_sync[AW-1:0]) &
(wr_addr[AW] != rd_addr_sync[AW]); (wr_addr_gray[AW] != rd_addr_gray_sync[AW]);
//########################### //###########################
//# Memory Array //# Memory Array
@ -158,6 +139,17 @@ module oh_fifo_async
.SHAPE(SHAPE)) .SHAPE(SHAPE))
oh_dpram(.wr_wem ({(N){1'b1}}), oh_dpram(.wr_wem ({(N){1'b1}}),
.wr_en (fifo_write), .wr_en (fifo_write),
.memconfig (8'b0),
.memrepair (8'b0),
.shutdown (1'b0),
.vddio (1'b1),
.vdd (1'b0),
.vss (1'b0),
.bist_en (1'b0),
.bist_we (1'b0),
.bist_wem ({(N){1'b0}}),
.bist_addr ({(AW){1'b0}}),
.bist_din ({(N){1'b0}}),
/*AUTOINST*/ /*AUTOINST*/
// Outputs // Outputs
.rd_dout (rd_dout[N-1:0]), .rd_dout (rd_dout[N-1:0]),
@ -167,17 +159,6 @@ module oh_fifo_async
.wr_din (wr_din[N-1:0]), .wr_din (wr_din[N-1:0]),
.rd_clk (rd_clk), .rd_clk (rd_clk),
.rd_en (rd_en), .rd_en (rd_en),
.rd_addr (rd_addr[AW-1:0]), .rd_addr (rd_addr[AW-1:0]));
.bist_en (bist_en),
.bist_we (bist_we),
.bist_wem (bist_wem[N-1:0]),
.bist_addr (bist_addr[AW-1:0]),
.bist_din (bist_din[N-1:0]),
.shutdown (shutdown),
.vss (vss),
.vdd (vdd),
.vddio (vddio),
.memconfig (memconfig[7:0]),
.memrepair (memrepair[7:0]));
endmodule // oh_fifo_async endmodule // oh_fifo_async

19
stdlib/rtl/oh_fifo_cdc.v
View File

@ -57,25 +57,12 @@ module oh_fifo_cdc
// parametric async fifo // parametric async fifo
oh_fifo_async #(.TARGET(TARGET), oh_fifo_async #(.TARGET(TARGET),
.N(N), .DEPTH(DEPTH),
.DEPTH(DEPTH)) .N(N))
oh_fifo_async ( oh_fifo_async (.rd_clk (clk_out),
.rd_clk (clk_out),
.rd_dout (packet_out[N-1:0]), .rd_dout (packet_out[N-1:0]),
.wr_clk (clk_in), .wr_clk (clk_in),
.wr_din (packet_in[N-1:0]), .wr_din (packet_in[N-1:0]),
.memconfig (8'b0),
.memrepair (8'b0),
.shutdown (1'b0),
.vddio (1'b1),
.vdd (1'b0),
.vss (1'b0),
.bist_en (1'b0),
.bist_we (1'b0),
.bist_wem ({(N){1'b0}}),
.bist_addr ({(AW){1'b0}}),
.bist_din ({(N){1'b0}}),
.bist_dout (),
.wr_count (), .wr_count (),
.rd_count (), .rd_count (),
.rd_empty (empty), .rd_empty (empty),