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Adding notes on generate blocksx

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Andreas Olofsson 2016-05-05 23:35:13 -04:00
parent 23cdb8d8d4
commit 59d758d9c6
1 changed files with 3 additions and 1 deletions
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README.md
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@ -123,10 +123,12 @@ TBD
* Use common names: nreset, clk, din, dout, en, rd, wr, addr, etc
* Make names descriptive, avoid non-common abbreviations
* Make names as short as possible, but not shorter
* Use short named generate blocks "g0, g1, etc"
* Inside generate blocks use short "i<name>" for instance
* Use _ in constants over 4 bits (eg: 8'h1100_1100)
* One module per file
* Use ".vh" suffix for header files,
* yse ".v" for verilog source files
* Use ".v" for verilog source files
* Use `include files for constants
* Use `ifndef _CONSTANTS_V to include file only once
* No timescales in design files (only in testbench)