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Compilation cleanup

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aolofsson 2021-07-24 23:29:50 -04:00
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commit 59e8d046da
17 changed files with 423 additions and 508 deletions
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58
common/hdl/oh_7seg_decode.v
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@ -2,38 +2,38 @@
//# Function: BCD Seven Segment Decoderh #
//#############################################################################
//# Author: Andreas Olofsson #
//# License: MIT (see LICENSE file in OH! repository) #
//# License: MIT (see LICENSE file in OH! repository) #
//#############################################################################
module oh_7seg_decode ( input [3:0] bcd, //0-9
output a, //a segment (1=0ff)
output b, //b segment
output c, //c segment
output d, //d segment
output e, //e segment
output f, //f segment
output g //g segment
);
module oh_7seg_decode
( input [3:0] bcd, //0-9
output a, //a segment (1=0ff)
output b, //b segment
output c, //c segment
output d, //d segment
output e, //e segment
output f, //f segment
output g //g segment
);
reg a,b,c,d,e,f,g;
always @ (*)
case(bcd[3:0])
4'h0 : {a,b,c,d,e,f,g} = 7'b0000001;
4'h1 : {a,b,c,d,e,f,g} = 7'b1001111;
4'h2 : {a,b,c,d,e,f,g} = 7'b0010010;
4'h3 : {a,b,c,d,e,f,g} = 7'b0000110;
4'h4 : {a,b,c,d,e,f,g} = 7'b1001100;
4'h5 : {a,b,c,d,e,f,g} = 7'b0100100;
4'h6 : {a,b,c,d,e,f,g} = 7'b0100000;
4'h7 : {a,b,c,d,e,f,g} = 7'b0001111;
4'h8 : {a,b,c,d,e,f,g} = 7'b0000000;
4'h9 : {a,b,c,d,e,f,g} = 7'b0001100;
default : {a,b,c,d,e,f,g} = 7'b1111111;
endcase // case (in[3:0])
endmodule
assign a = (bcd[3:0] == 4'h1) | (bcd[3:0] == 4'h4);
assign b = (bcd[3:0] == 4'h5) | (bcd[3:0] == 4'h6);
assign c = (bcd[3:0] == 4'h2);
assign d = (bcd[3:0] == 4'h1) | (bcd[3:0] == 4'h4)|
(bcd[3:0] == 4'h7) | (bcd[3:0] == 4'h9);
assign e = (bcd[3:0] == 4'h1) | (bcd[3:0] == 4'h3)|
(bcd[3:0] == 4'h4) | (bcd[3:0] == 4'h5)|
(bcd[3:0] == 4'h7) | (bcd[3:0] == 4'h9);
assign f = (bcd[3:0] == 4'h1) | (bcd[3:0] == 4'h2)|
(bcd[3:0] == 4'h3) | (bcd[3:0] == 4'h7);
assign g = (bcd[3:0] == 4'h0) | (bcd[3:0] == 4'h1) |
(bcd[3:0] == 4'h7);
endmodule // oh_7seg_decode

25
common/hdl/oh_bitreverse.v
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@ -2,7 +2,7 @@
//# Function: Binary to one hot encoder #
//#############################################################################
//# Author: Andreas Olofsson #
//# License: MIT (see LICENSE file in OH! repository) #
//# License: MIT (see LICENSE file in OH! repository) #
//#############################################################################
module oh_bitreverse #(parameter DW = 32 // width of data inputs
@ -11,19 +11,12 @@ module oh_bitreverse #(parameter DW = 32 // width of data inputs
input [DW-1:0] in, // data input
output [DW-1:0] out // bit reversed output
);
reg [DW-1:0] out;
integer i;
always @*
for (i=0;i<DW;i=i+1)
out[i]=in[DW-1-i];
genvar i;
generate
for (i=0;i<DW;i=i+1)
assign out[i] = in[DW-1-i];
endgenerate
endmodule // oh_bitreverse

43
common/hdl/oh_counter.v
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@ -2,49 +2,42 @@
//# Function: Generic counter #
//#############################################################################
//# Author: Andreas Olofsson #
//# License: MIT (see LICENSE file in OH! repository) #
//# License: MIT (see LICENSE file in OH! repository) #
//#############################################################################
module oh_counter #(parameter DW = 32 // width of data inputs
)
module oh_counter
#(parameter DW = 32 // width of data inputs
)
(
//inputs
input clk, // clk input
input in, // input to count
input en, // enable counter
input dir,//0=increment, 1=decrement
input autowrap, //auto wrap around
input load, // load counter
input [DW-1:0] load_data, // input data to load
input clk, // clk input
input in, // input to count
input en, // enable counter
input dir,//0=increment, 1=decrement
input autowrap, //auto wrap around
input load, // load counter
input [DW-1:0] load_data, // input data to load
//outputs
output [DW-1:0] count, // count value
output wraparound // wraparound indicator
output reg [DW-1:0] count, // count value
output wraparound // wraparound indicator
);
// local variables
reg [DW-1:0] count;
wire [DW-1:0] count_in;
//Select count direction
assign count_in[DW-1:0] = dir ? count[DW-1:0] - in :
count[DW-1:0] + in ;
// counter
always @(posedge clk)
if(load)
count[DW-1:0] <= load_data[DW-1:0];
else if (en & ~(wraparound & ~autowrap))
count[DW-1:0] <= count_in[DW-1:0];
// counter expired
assign wraparound = (dir & en & ~(|count[DW-1:0])) |
(~dir & en & (&count[DW-1:0]));
endmodule // oh_counter

40
common/hdl/oh_crc.v
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@ -1,40 +0,0 @@
//#############################################################################
//# Function: CRC combinatorial encoder wrapper #
//#############################################################################
//# Author: Andreas Olofsson #
//# License: MIT (see LICENSE file in OH! repository) #
//#############################################################################
module oh_crc #( parameter TYPE = "ETH", // type: "ETH", "OTHER"
parameter DW = 8) // width of data
(
input [DW-1:0] data_in, // input data
input [CW-1:0] crc_state, // input crc state
output [CW-1:0] crc_next // next crc state
);
localparam CW = 32; // width of polynomial
generate
if(TYPE=="ETH")
begin
if(DW==8)
oh_crc32_8b crc(/*AUTOINST*/
// Outputs
.crc_next (crc_next[31:0]),
// Inputs
.data_in (data_in[7:0]),
.crc_state (crc_state[31:0]));
else if(DW==64)
oh_crc32_64b crc(/*AUTOINST*/
// Outputs
.crc_next (crc_next[31:0]),
// Inputs
.data_in (data_in[63:0]),
.crc_state (crc_state[31:0]));
end // if (TYPE=="ETH")
endgenerate
endmodule // oh_crc

79
common/hdl/oh_crc32_64b.v
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@ -1,79 +0,0 @@
/*
* CRC module eth_crc_64 (see license below)
*
* CRC width: 32
* Data width: 64
* CRC polynomial: 32'h4c11db7
* Configuration: galois
* Bit-reverse: input and output
*
* x^32 + x^26 + x^23 + x^22 + x^16 + x^12 + x^11 + x^10 + x^8 + x^7 + x^5 + x^4 + x^2 + x + 1
*
* Generated by https://github.com/alexforencich/fpga-utils/blob/master/crcgen.py/crcgen.py
*
* crcgen.py -b -r -d 64 -n eth_crc_64
*
*/
module oh_crc32_64b(/*AUTOARG*/
// Outputs
crc_next,
// Inputs
data_in, crc_state
);
input [63:0] data_in;
input [31:0] crc_state;
output [31:0] crc_next;
assign crc_next[0] = crc_state[1] ^ crc_state[3] ^ crc_state[4] ^ crc_state[6] ^ crc_state[9] ^ crc_state[10] ^ crc_state[11] ^ crc_state[14] ^ crc_state[16] ^ crc_state[17] ^ crc_state[19] ^ crc_state[20] ^ crc_state[27] ^ crc_state[30] ^ data_in[1] ^ data_in[3] ^ data_in[4] ^ data_in[6] ^ data_in[9] ^ data_in[10] ^ data_in[11] ^ data_in[14] ^ data_in[16] ^ data_in[17] ^ data_in[19] ^ data_in[20] ^ data_in[27] ^ data_in[30] ^ data_in[32] ^ data_in[33] ^ data_in[34] ^ data_in[35] ^ data_in[36] ^ data_in[38] ^ data_in[39] ^ data_in[40] ^ data_in[48] ^ data_in[52] ^ data_in[54] ^ data_in[55] ^ data_in[58];
assign crc_next[1] = crc_state[0] ^ crc_state[2] ^ crc_state[4] ^ crc_state[5] ^ crc_state[7] ^ crc_state[10] ^ crc_state[11] ^ crc_state[12] ^ crc_state[15] ^ crc_state[17] ^ crc_state[18] ^ crc_state[20] ^ crc_state[21] ^ crc_state[28] ^ crc_state[31] ^ data_in[0] ^ data_in[2] ^ data_in[4] ^ data_in[5] ^ data_in[7] ^ data_in[10] ^ data_in[11] ^ data_in[12] ^ data_in[15] ^ data_in[17] ^ data_in[18] ^ data_in[20] ^ data_in[21] ^ data_in[28] ^ data_in[31] ^ data_in[33] ^ data_in[34] ^ data_in[35] ^ data_in[36] ^ data_in[37] ^ data_in[39] ^ data_in[40] ^ data_in[41] ^ data_in[49] ^ data_in[53] ^ data_in[55] ^ data_in[56] ^ data_in[59];
assign crc_next[2] = crc_state[0] ^ crc_state[1] ^ crc_state[3] ^ crc_state[5] ^ crc_state[6] ^ crc_state[8] ^ crc_state[11] ^ crc_state[12] ^ crc_state[13] ^ crc_state[16] ^ crc_state[18] ^ crc_state[19] ^ crc_state[21] ^ crc_state[22] ^ crc_state[29] ^ data_in[0] ^ data_in[1] ^ data_in[3] ^ data_in[5] ^ data_in[6] ^ data_in[8] ^ data_in[11] ^ data_in[12] ^ data_in[13] ^ data_in[16] ^ data_in[18] ^ data_in[19] ^ data_in[21] ^ data_in[22] ^ data_in[29] ^ data_in[32] ^ data_in[34] ^ data_in[35] ^ data_in[36] ^ data_in[37] ^ data_in[38] ^ data_in[40] ^ data_in[41] ^ data_in[42] ^ data_in[50] ^ data_in[54] ^ data_in[56] ^ data_in[57] ^ data_in[60];
assign crc_next[3] = crc_state[0] ^ crc_state[1] ^ crc_state[2] ^ crc_state[4] ^ crc_state[6] ^ crc_state[7] ^ crc_state[9] ^ crc_state[12] ^ crc_state[13] ^ crc_state[14] ^ crc_state[17] ^ crc_state[19] ^ crc_state[20] ^ crc_state[22] ^ crc_state[23] ^ crc_state[30] ^ data_in[0] ^ data_in[1] ^ data_in[2] ^ data_in[4] ^ data_in[6] ^ data_in[7] ^ data_in[9] ^ data_in[12] ^ data_in[13] ^ data_in[14] ^ data_in[17] ^ data_in[19] ^ data_in[20] ^ data_in[22] ^ data_in[23] ^ data_in[30] ^ data_in[33] ^ data_in[35] ^ data_in[36] ^ data_in[37] ^ data_in[38] ^ data_in[39] ^ data_in[41] ^ data_in[42] ^ data_in[43] ^ data_in[51] ^ data_in[55] ^ data_in[57] ^ data_in[58] ^ data_in[61];
assign crc_next[4] = crc_state[0] ^ crc_state[1] ^ crc_state[2] ^ crc_state[3] ^ crc_state[5] ^ crc_state[7] ^ crc_state[8] ^ crc_state[10] ^ crc_state[13] ^ crc_state[14] ^ crc_state[15] ^ crc_state[18] ^ crc_state[20] ^ crc_state[21] ^ crc_state[23] ^ crc_state[24] ^ crc_state[31] ^ data_in[0] ^ data_in[1] ^ data_in[2] ^ data_in[3] ^ data_in[5] ^ data_in[7] ^ data_in[8] ^ data_in[10] ^ data_in[13] ^ data_in[14] ^ data_in[15] ^ data_in[18] ^ data_in[20] ^ data_in[21] ^ data_in[23] ^ data_in[24] ^ data_in[31] ^ data_in[34] ^ data_in[36] ^ data_in[37] ^ data_in[38] ^ data_in[39] ^ data_in[40] ^ data_in[42] ^ data_in[43] ^ data_in[44] ^ data_in[52] ^ data_in[56] ^ data_in[58] ^ data_in[59] ^ data_in[62];
assign crc_next[5] = crc_state[1] ^ crc_state[2] ^ crc_state[3] ^ crc_state[4] ^ crc_state[6] ^ crc_state[8] ^ crc_state[9] ^ crc_state[11] ^ crc_state[14] ^ crc_state[15] ^ crc_state[16] ^ crc_state[19] ^ crc_state[21] ^ crc_state[22] ^ crc_state[24] ^ crc_state[25] ^ data_in[1] ^ data_in[2] ^ data_in[3] ^ data_in[4] ^ data_in[6] ^ data_in[8] ^ data_in[9] ^ data_in[11] ^ data_in[14] ^ data_in[15] ^ data_in[16] ^ data_in[19] ^ data_in[21] ^ data_in[22] ^ data_in[24] ^ data_in[25] ^ data_in[32] ^ data_in[35] ^ data_in[37] ^ data_in[38] ^ data_in[39] ^ data_in[40] ^ data_in[41] ^ data_in[43] ^ data_in[44] ^ data_in[45] ^ data_in[53] ^ data_in[57] ^ data_in[59] ^ data_in[60] ^ data_in[63];
assign crc_next[6] = crc_state[1] ^ crc_state[2] ^ crc_state[5] ^ crc_state[6] ^ crc_state[7] ^ crc_state[11] ^ crc_state[12] ^ crc_state[14] ^ crc_state[15] ^ crc_state[19] ^ crc_state[22] ^ crc_state[23] ^ crc_state[25] ^ crc_state[26] ^ crc_state[27] ^ crc_state[30] ^ data_in[1] ^ data_in[2] ^ data_in[5] ^ data_in[6] ^ data_in[7] ^ data_in[11] ^ data_in[12] ^ data_in[14] ^ data_in[15] ^ data_in[19] ^ data_in[22] ^ data_in[23] ^ data_in[25] ^ data_in[26] ^ data_in[27] ^ data_in[30] ^ data_in[32] ^ data_in[34] ^ data_in[35] ^ data_in[41] ^ data_in[42] ^ data_in[44] ^ data_in[45] ^ data_in[46] ^ data_in[48] ^ data_in[52] ^ data_in[55] ^ data_in[60] ^ data_in[61];
assign crc_next[7] = crc_state[0] ^ crc_state[2] ^ crc_state[3] ^ crc_state[6] ^ crc_state[7] ^ crc_state[8] ^ crc_state[12] ^ crc_state[13] ^ crc_state[15] ^ crc_state[16] ^ crc_state[20] ^ crc_state[23] ^ crc_state[24] ^ crc_state[26] ^ crc_state[27] ^ crc_state[28] ^ crc_state[31] ^ data_in[0] ^ data_in[2] ^ data_in[3] ^ data_in[6] ^ data_in[7] ^ data_in[8] ^ data_in[12] ^ data_in[13] ^ data_in[15] ^ data_in[16] ^ data_in[20] ^ data_in[23] ^ data_in[24] ^ data_in[26] ^ data_in[27] ^ data_in[28] ^ data_in[31] ^ data_in[33] ^ data_in[35] ^ data_in[36] ^ data_in[42] ^ data_in[43] ^ data_in[45] ^ data_in[46] ^ data_in[47] ^ data_in[49] ^ data_in[53] ^ data_in[56] ^ data_in[61] ^ data_in[62];
assign crc_next[8] = crc_state[1] ^ crc_state[3] ^ crc_state[4] ^ crc_state[7] ^ crc_state[8] ^ crc_state[9] ^ crc_state[13] ^ crc_state[14] ^ crc_state[16] ^ crc_state[17] ^ crc_state[21] ^ crc_state[24] ^ crc_state[25] ^ crc_state[27] ^ crc_state[28] ^ crc_state[29] ^ data_in[1] ^ data_in[3] ^ data_in[4] ^ data_in[7] ^ data_in[8] ^ data_in[9] ^ data_in[13] ^ data_in[14] ^ data_in[16] ^ data_in[17] ^ data_in[21] ^ data_in[24] ^ data_in[25] ^ data_in[27] ^ data_in[28] ^ data_in[29] ^ data_in[32] ^ data_in[34] ^ data_in[36] ^ data_in[37] ^ data_in[43] ^ data_in[44] ^ data_in[46] ^ data_in[47] ^ data_in[48] ^ data_in[50] ^ data_in[54] ^ data_in[57] ^ data_in[62] ^ data_in[63];
assign crc_next[9] = crc_state[1] ^ crc_state[2] ^ crc_state[3] ^ crc_state[5] ^ crc_state[6] ^ crc_state[8] ^ crc_state[11] ^ crc_state[15] ^ crc_state[16] ^ crc_state[18] ^ crc_state[19] ^ crc_state[20] ^ crc_state[22] ^ crc_state[25] ^ crc_state[26] ^ crc_state[27] ^ crc_state[28] ^ crc_state[29] ^ data_in[1] ^ data_in[2] ^ data_in[3] ^ data_in[5] ^ data_in[6] ^ data_in[8] ^ data_in[11] ^ data_in[15] ^ data_in[16] ^ data_in[18] ^ data_in[19] ^ data_in[20] ^ data_in[22] ^ data_in[25] ^ data_in[26] ^ data_in[27] ^ data_in[28] ^ data_in[29] ^ data_in[32] ^ data_in[34] ^ data_in[36] ^ data_in[37] ^ data_in[39] ^ data_in[40] ^ data_in[44] ^ data_in[45] ^ data_in[47] ^ data_in[49] ^ data_in[51] ^ data_in[52] ^ data_in[54] ^ data_in[63];
assign crc_next[10] = crc_state[1] ^ crc_state[2] ^ crc_state[7] ^ crc_state[10] ^ crc_state[11] ^ crc_state[12] ^ crc_state[14] ^ crc_state[21] ^ crc_state[23] ^ crc_state[26] ^ crc_state[28] ^ crc_state[29] ^ data_in[1] ^ data_in[2] ^ data_in[7] ^ data_in[10] ^ data_in[11] ^ data_in[12] ^ data_in[14] ^ data_in[21] ^ data_in[23] ^ data_in[26] ^ data_in[28] ^ data_in[29] ^ data_in[32] ^ data_in[34] ^ data_in[36] ^ data_in[37] ^ data_in[39] ^ data_in[41] ^ data_in[45] ^ data_in[46] ^ data_in[50] ^ data_in[53] ^ data_in[54] ^ data_in[58];
assign crc_next[11] = crc_state[2] ^ crc_state[3] ^ crc_state[8] ^ crc_state[11] ^ crc_state[12] ^ crc_state[13] ^ crc_state[15] ^ crc_state[22] ^ crc_state[24] ^ crc_state[27] ^ crc_state[29] ^ crc_state[30] ^ data_in[2] ^ data_in[3] ^ data_in[8] ^ data_in[11] ^ data_in[12] ^ data_in[13] ^ data_in[15] ^ data_in[22] ^ data_in[24] ^ data_in[27] ^ data_in[29] ^ data_in[30] ^ data_in[33] ^ data_in[35] ^ data_in[37] ^ data_in[38] ^ data_in[40] ^ data_in[42] ^ data_in[46] ^ data_in[47] ^ data_in[51] ^ data_in[54] ^ data_in[55] ^ data_in[59];
assign crc_next[12] = crc_state[3] ^ crc_state[4] ^ crc_state[9] ^ crc_state[12] ^ crc_state[13] ^ crc_state[14] ^ crc_state[16] ^ crc_state[23] ^ crc_state[25] ^ crc_state[28] ^ crc_state[30] ^ crc_state[31] ^ data_in[3] ^ data_in[4] ^ data_in[9] ^ data_in[12] ^ data_in[13] ^ data_in[14] ^ data_in[16] ^ data_in[23] ^ data_in[25] ^ data_in[28] ^ data_in[30] ^ data_in[31] ^ data_in[34] ^ data_in[36] ^ data_in[38] ^ data_in[39] ^ data_in[41] ^ data_in[43] ^ data_in[47] ^ data_in[48] ^ data_in[52] ^ data_in[55] ^ data_in[56] ^ data_in[60];
assign crc_next[13] = crc_state[4] ^ crc_state[5] ^ crc_state[10] ^ crc_state[13] ^ crc_state[14] ^ crc_state[15] ^ crc_state[17] ^ crc_state[24] ^ crc_state[26] ^ crc_state[29] ^ crc_state[31] ^ data_in[4] ^ data_in[5] ^ data_in[10] ^ data_in[13] ^ data_in[14] ^ data_in[15] ^ data_in[17] ^ data_in[24] ^ data_in[26] ^ data_in[29] ^ data_in[31] ^ data_in[32] ^ data_in[35] ^ data_in[37] ^ data_in[39] ^ data_in[40] ^ data_in[42] ^ data_in[44] ^ data_in[48] ^ data_in[49] ^ data_in[53] ^ data_in[56] ^ data_in[57] ^ data_in[61];
assign crc_next[14] = crc_state[5] ^ crc_state[6] ^ crc_state[11] ^ crc_state[14] ^ crc_state[15] ^ crc_state[16] ^ crc_state[18] ^ crc_state[25] ^ crc_state[27] ^ crc_state[30] ^ data_in[5] ^ data_in[6] ^ data_in[11] ^ data_in[14] ^ data_in[15] ^ data_in[16] ^ data_in[18] ^ data_in[25] ^ data_in[27] ^ data_in[30] ^ data_in[32] ^ data_in[33] ^ data_in[36] ^ data_in[38] ^ data_in[40] ^ data_in[41] ^ data_in[43] ^ data_in[45] ^ data_in[49] ^ data_in[50] ^ data_in[54] ^ data_in[57] ^ data_in[58] ^ data_in[62];
assign crc_next[15] = crc_state[6] ^ crc_state[7] ^ crc_state[12] ^ crc_state[15] ^ crc_state[16] ^ crc_state[17] ^ crc_state[19] ^ crc_state[26] ^ crc_state[28] ^ crc_state[31] ^ data_in[6] ^ data_in[7] ^ data_in[12] ^ data_in[15] ^ data_in[16] ^ data_in[17] ^ data_in[19] ^ data_in[26] ^ data_in[28] ^ data_in[31] ^ data_in[33] ^ data_in[34] ^ data_in[37] ^ data_in[39] ^ data_in[41] ^ data_in[42] ^ data_in[44] ^ data_in[46] ^ data_in[50] ^ data_in[51] ^ data_in[55] ^ data_in[58] ^ data_in[59] ^ data_in[63];
assign crc_next[16] = crc_state[1] ^ crc_state[3] ^ crc_state[4] ^ crc_state[6] ^ crc_state[7] ^ crc_state[8] ^ crc_state[9] ^ crc_state[10] ^ crc_state[11] ^ crc_state[13] ^ crc_state[14] ^ crc_state[18] ^ crc_state[19] ^ crc_state[29] ^ crc_state[30] ^ data_in[1] ^ data_in[3] ^ data_in[4] ^ data_in[6] ^ data_in[7] ^ data_in[8] ^ data_in[9] ^ data_in[10] ^ data_in[11] ^ data_in[13] ^ data_in[14] ^ data_in[18] ^ data_in[19] ^ data_in[29] ^ data_in[30] ^ data_in[33] ^ data_in[36] ^ data_in[39] ^ data_in[42] ^ data_in[43] ^ data_in[45] ^ data_in[47] ^ data_in[48] ^ data_in[51] ^ data_in[54] ^ data_in[55] ^ data_in[56] ^ data_in[58] ^ data_in[59] ^ data_in[60];
assign crc_next[17] = crc_state[0] ^ crc_state[2] ^ crc_state[4] ^ crc_state[5] ^ crc_state[7] ^ crc_state[8] ^ crc_state[9] ^ crc_state[10] ^ crc_state[11] ^ crc_state[12] ^ crc_state[14] ^ crc_state[15] ^ crc_state[19] ^ crc_state[20] ^ crc_state[30] ^ crc_state[31] ^ data_in[0] ^ data_in[2] ^ data_in[4] ^ data_in[5] ^ data_in[7] ^ data_in[8] ^ data_in[9] ^ data_in[10] ^ data_in[11] ^ data_in[12] ^ data_in[14] ^ data_in[15] ^ data_in[19] ^ data_in[20] ^ data_in[30] ^ data_in[31] ^ data_in[34] ^ data_in[37] ^ data_in[40] ^ data_in[43] ^ data_in[44] ^ data_in[46] ^ data_in[48] ^ data_in[49] ^ data_in[52] ^ data_in[55] ^ data_in[56] ^ data_in[57] ^ data_in[59] ^ data_in[60] ^ data_in[61];
assign crc_next[18] = crc_state[1] ^ crc_state[3] ^ crc_state[5] ^ crc_state[6] ^ crc_state[8] ^ crc_state[9] ^ crc_state[10] ^ crc_state[11] ^ crc_state[12] ^ crc_state[13] ^ crc_state[15] ^ crc_state[16] ^ crc_state[20] ^ crc_state[21] ^ crc_state[31] ^ data_in[1] ^ data_in[3] ^ data_in[5] ^ data_in[6] ^ data_in[8] ^ data_in[9] ^ data_in[10] ^ data_in[11] ^ data_in[12] ^ data_in[13] ^ data_in[15] ^ data_in[16] ^ data_in[20] ^ data_in[21] ^ data_in[31] ^ data_in[32] ^ data_in[35] ^ data_in[38] ^ data_in[41] ^ data_in[44] ^ data_in[45] ^ data_in[47] ^ data_in[49] ^ data_in[50] ^ data_in[53] ^ data_in[56] ^ data_in[57] ^ data_in[58] ^ data_in[60] ^ data_in[61] ^ data_in[62];
assign crc_next[19] = crc_state[0] ^ crc_state[2] ^ crc_state[4] ^ crc_state[6] ^ crc_state[7] ^ crc_state[9] ^ crc_state[10] ^ crc_state[11] ^ crc_state[12] ^ crc_state[13] ^ crc_state[14] ^ crc_state[16] ^ crc_state[17] ^ crc_state[21] ^ crc_state[22] ^ data_in[0] ^ data_in[2] ^ data_in[4] ^ data_in[6] ^ data_in[7] ^ data_in[9] ^ data_in[10] ^ data_in[11] ^ data_in[12] ^ data_in[13] ^ data_in[14] ^ data_in[16] ^ data_in[17] ^ data_in[21] ^ data_in[22] ^ data_in[32] ^ data_in[33] ^ data_in[36] ^ data_in[39] ^ data_in[42] ^ data_in[45] ^ data_in[46] ^ data_in[48] ^ data_in[50] ^ data_in[51] ^ data_in[54] ^ data_in[57] ^ data_in[58] ^ data_in[59] ^ data_in[61] ^ data_in[62] ^ data_in[63];
assign crc_next[20] = crc_state[4] ^ crc_state[5] ^ crc_state[6] ^ crc_state[7] ^ crc_state[8] ^ crc_state[9] ^ crc_state[12] ^ crc_state[13] ^ crc_state[15] ^ crc_state[16] ^ crc_state[18] ^ crc_state[19] ^ crc_state[20] ^ crc_state[22] ^ crc_state[23] ^ crc_state[27] ^ crc_state[30] ^ data_in[4] ^ data_in[5] ^ data_in[6] ^ data_in[7] ^ data_in[8] ^ data_in[9] ^ data_in[12] ^ data_in[13] ^ data_in[15] ^ data_in[16] ^ data_in[18] ^ data_in[19] ^ data_in[20] ^ data_in[22] ^ data_in[23] ^ data_in[27] ^ data_in[30] ^ data_in[32] ^ data_in[35] ^ data_in[36] ^ data_in[37] ^ data_in[38] ^ data_in[39] ^ data_in[43] ^ data_in[46] ^ data_in[47] ^ data_in[48] ^ data_in[49] ^ data_in[51] ^ data_in[54] ^ data_in[59] ^ data_in[60] ^ data_in[62] ^ data_in[63];
assign crc_next[21] = crc_state[0] ^ crc_state[1] ^ crc_state[3] ^ crc_state[4] ^ crc_state[5] ^ crc_state[7] ^ crc_state[8] ^ crc_state[11] ^ crc_state[13] ^ crc_state[21] ^ crc_state[23] ^ crc_state[24] ^ crc_state[27] ^ crc_state[28] ^ crc_state[30] ^ crc_state[31] ^ data_in[0] ^ data_in[1] ^ data_in[3] ^ data_in[4] ^ data_in[5] ^ data_in[7] ^ data_in[8] ^ data_in[11] ^ data_in[13] ^ data_in[21] ^ data_in[23] ^ data_in[24] ^ data_in[27] ^ data_in[28] ^ data_in[30] ^ data_in[31] ^ data_in[32] ^ data_in[34] ^ data_in[35] ^ data_in[37] ^ data_in[44] ^ data_in[47] ^ data_in[49] ^ data_in[50] ^ data_in[54] ^ data_in[58] ^ data_in[60] ^ data_in[61] ^ data_in[63];
assign crc_next[22] = crc_state[2] ^ crc_state[3] ^ crc_state[5] ^ crc_state[8] ^ crc_state[10] ^ crc_state[11] ^ crc_state[12] ^ crc_state[16] ^ crc_state[17] ^ crc_state[19] ^ crc_state[20] ^ crc_state[22] ^ crc_state[24] ^ crc_state[25] ^ crc_state[27] ^ crc_state[28] ^ crc_state[29] ^ crc_state[30] ^ crc_state[31] ^ data_in[2] ^ data_in[3] ^ data_in[5] ^ data_in[8] ^ data_in[10] ^ data_in[11] ^ data_in[12] ^ data_in[16] ^ data_in[17] ^ data_in[19] ^ data_in[20] ^ data_in[22] ^ data_in[24] ^ data_in[25] ^ data_in[27] ^ data_in[28] ^ data_in[29] ^ data_in[30] ^ data_in[31] ^ data_in[34] ^ data_in[39] ^ data_in[40] ^ data_in[45] ^ data_in[50] ^ data_in[51] ^ data_in[52] ^ data_in[54] ^ data_in[58] ^ data_in[59] ^ data_in[61] ^ data_in[62];
assign crc_next[23] = crc_state[0] ^ crc_state[3] ^ crc_state[4] ^ crc_state[6] ^ crc_state[9] ^ crc_state[11] ^ crc_state[12] ^ crc_state[13] ^ crc_state[17] ^ crc_state[18] ^ crc_state[20] ^ crc_state[21] ^ crc_state[23] ^ crc_state[25] ^ crc_state[26] ^ crc_state[28] ^ crc_state[29] ^ crc_state[30] ^ crc_state[31] ^ data_in[0] ^ data_in[3] ^ data_in[4] ^ data_in[6] ^ data_in[9] ^ data_in[11] ^ data_in[12] ^ data_in[13] ^ data_in[17] ^ data_in[18] ^ data_in[20] ^ data_in[21] ^ data_in[23] ^ data_in[25] ^ data_in[26] ^ data_in[28] ^ data_in[29] ^ data_in[30] ^ data_in[31] ^ data_in[32] ^ data_in[35] ^ data_in[40] ^ data_in[41] ^ data_in[46] ^ data_in[51] ^ data_in[52] ^ data_in[53] ^ data_in[55] ^ data_in[59] ^ data_in[60] ^ data_in[62] ^ data_in[63];
assign crc_next[24] = crc_state[3] ^ crc_state[5] ^ crc_state[6] ^ crc_state[7] ^ crc_state[9] ^ crc_state[11] ^ crc_state[12] ^ crc_state[13] ^ crc_state[16] ^ crc_state[17] ^ crc_state[18] ^ crc_state[20] ^ crc_state[21] ^ crc_state[22] ^ crc_state[24] ^ crc_state[26] ^ crc_state[29] ^ crc_state[31] ^ data_in[3] ^ data_in[5] ^ data_in[6] ^ data_in[7] ^ data_in[9] ^ data_in[11] ^ data_in[12] ^ data_in[13] ^ data_in[16] ^ data_in[17] ^ data_in[18] ^ data_in[20] ^ data_in[21] ^ data_in[22] ^ data_in[24] ^ data_in[26] ^ data_in[29] ^ data_in[31] ^ data_in[34] ^ data_in[35] ^ data_in[38] ^ data_in[39] ^ data_in[40] ^ data_in[41] ^ data_in[42] ^ data_in[47] ^ data_in[48] ^ data_in[53] ^ data_in[55] ^ data_in[56] ^ data_in[58] ^ data_in[60] ^ data_in[61] ^ data_in[63];
assign crc_next[25] = crc_state[1] ^ crc_state[3] ^ crc_state[7] ^ crc_state[8] ^ crc_state[9] ^ crc_state[11] ^ crc_state[12] ^ crc_state[13] ^ crc_state[16] ^ crc_state[18] ^ crc_state[20] ^ crc_state[21] ^ crc_state[22] ^ crc_state[23] ^ crc_state[25] ^ data_in[1] ^ data_in[3] ^ data_in[7] ^ data_in[8] ^ data_in[9] ^ data_in[11] ^ data_in[12] ^ data_in[13] ^ data_in[16] ^ data_in[18] ^ data_in[20] ^ data_in[21] ^ data_in[22] ^ data_in[23] ^ data_in[25] ^ data_in[33] ^ data_in[34] ^ data_in[38] ^ data_in[41] ^ data_in[42] ^ data_in[43] ^ data_in[49] ^ data_in[52] ^ data_in[55] ^ data_in[56] ^ data_in[57] ^ data_in[58] ^ data_in[59] ^ data_in[61] ^ data_in[62];
assign crc_next[26] = crc_state[0] ^ crc_state[2] ^ crc_state[4] ^ crc_state[8] ^ crc_state[9] ^ crc_state[10] ^ crc_state[12] ^ crc_state[13] ^ crc_state[14] ^ crc_state[17] ^ crc_state[19] ^ crc_state[21] ^ crc_state[22] ^ crc_state[23] ^ crc_state[24] ^ crc_state[26] ^ data_in[0] ^ data_in[2] ^ data_in[4] ^ data_in[8] ^ data_in[9] ^ data_in[10] ^ data_in[12] ^ data_in[13] ^ data_in[14] ^ data_in[17] ^ data_in[19] ^ data_in[21] ^ data_in[22] ^ data_in[23] ^ data_in[24] ^ data_in[26] ^ data_in[34] ^ data_in[35] ^ data_in[39] ^ data_in[42] ^ data_in[43] ^ data_in[44] ^ data_in[50] ^ data_in[53] ^ data_in[56] ^ data_in[57] ^ data_in[58] ^ data_in[59] ^ data_in[60] ^ data_in[62] ^ data_in[63];
assign crc_next[27] = crc_state[0] ^ crc_state[4] ^ crc_state[5] ^ crc_state[6] ^ crc_state[13] ^ crc_state[15] ^ crc_state[16] ^ crc_state[17] ^ crc_state[18] ^ crc_state[19] ^ crc_state[22] ^ crc_state[23] ^ crc_state[24] ^ crc_state[25] ^ crc_state[30] ^ data_in[0] ^ data_in[4] ^ data_in[5] ^ data_in[6] ^ data_in[13] ^ data_in[15] ^ data_in[16] ^ data_in[17] ^ data_in[18] ^ data_in[19] ^ data_in[22] ^ data_in[23] ^ data_in[24] ^ data_in[25] ^ data_in[30] ^ data_in[32] ^ data_in[33] ^ data_in[34] ^ data_in[38] ^ data_in[39] ^ data_in[43] ^ data_in[44] ^ data_in[45] ^ data_in[48] ^ data_in[51] ^ data_in[52] ^ data_in[55] ^ data_in[57] ^ data_in[59] ^ data_in[60] ^ data_in[61] ^ data_in[63];
assign crc_next[28] = crc_state[3] ^ crc_state[4] ^ crc_state[5] ^ crc_state[7] ^ crc_state[9] ^ crc_state[10] ^ crc_state[11] ^ crc_state[18] ^ crc_state[23] ^ crc_state[24] ^ crc_state[25] ^ crc_state[26] ^ crc_state[27] ^ crc_state[30] ^ crc_state[31] ^ data_in[3] ^ data_in[4] ^ data_in[5] ^ data_in[7] ^ data_in[9] ^ data_in[10] ^ data_in[11] ^ data_in[18] ^ data_in[23] ^ data_in[24] ^ data_in[25] ^ data_in[26] ^ data_in[27] ^ data_in[30] ^ data_in[31] ^ data_in[32] ^ data_in[36] ^ data_in[38] ^ data_in[44] ^ data_in[45] ^ data_in[46] ^ data_in[48] ^ data_in[49] ^ data_in[53] ^ data_in[54] ^ data_in[55] ^ data_in[56] ^ data_in[60] ^ data_in[61] ^ data_in[62];
assign crc_next[29] = crc_state[4] ^ crc_state[5] ^ crc_state[6] ^ crc_state[8] ^ crc_state[10] ^ crc_state[11] ^ crc_state[12] ^ crc_state[19] ^ crc_state[24] ^ crc_state[25] ^ crc_state[26] ^ crc_state[27] ^ crc_state[28] ^ crc_state[31] ^ data_in[4] ^ data_in[5] ^ data_in[6] ^ data_in[8] ^ data_in[10] ^ data_in[11] ^ data_in[12] ^ data_in[19] ^ data_in[24] ^ data_in[25] ^ data_in[26] ^ data_in[27] ^ data_in[28] ^ data_in[31] ^ data_in[32] ^ data_in[33] ^ data_in[37] ^ data_in[39] ^ data_in[45] ^ data_in[46] ^ data_in[47] ^ data_in[49] ^ data_in[50] ^ data_in[54] ^ data_in[55] ^ data_in[56] ^ data_in[57] ^ data_in[61] ^ data_in[62] ^ data_in[63];
assign crc_next[30] = crc_state[0] ^ crc_state[1] ^ crc_state[3] ^ crc_state[4] ^ crc_state[5] ^ crc_state[7] ^ crc_state[10] ^ crc_state[12] ^ crc_state[13] ^ crc_state[14] ^ crc_state[16] ^ crc_state[17] ^ crc_state[19] ^ crc_state[25] ^ crc_state[26] ^ crc_state[28] ^ crc_state[29] ^ crc_state[30] ^ data_in[0] ^ data_in[1] ^ data_in[3] ^ data_in[4] ^ data_in[5] ^ data_in[7] ^ data_in[10] ^ data_in[12] ^ data_in[13] ^ data_in[14] ^ data_in[16] ^ data_in[17] ^ data_in[19] ^ data_in[25] ^ data_in[26] ^ data_in[28] ^ data_in[29] ^ data_in[30] ^ data_in[35] ^ data_in[36] ^ data_in[39] ^ data_in[46] ^ data_in[47] ^ data_in[50] ^ data_in[51] ^ data_in[52] ^ data_in[54] ^ data_in[56] ^ data_in[57] ^ data_in[62] ^ data_in[63];
assign crc_next[31] = crc_state[0] ^ crc_state[2] ^ crc_state[3] ^ crc_state[5] ^ crc_state[8] ^ crc_state[9] ^ crc_state[10] ^ crc_state[13] ^ crc_state[15] ^ crc_state[16] ^ crc_state[18] ^ crc_state[19] ^ crc_state[26] ^ crc_state[29] ^ crc_state[31] ^ data_in[0] ^ data_in[2] ^ data_in[3] ^ data_in[5] ^ data_in[8] ^ data_in[9] ^ data_in[10] ^ data_in[13] ^ data_in[15] ^ data_in[16] ^ data_in[18] ^ data_in[19] ^ data_in[26] ^ data_in[29] ^ data_in[31] ^ data_in[32] ^ data_in[33] ^ data_in[34] ^ data_in[35] ^ data_in[37] ^ data_in[38] ^ data_in[39] ^ data_in[47] ^ data_in[51] ^ data_in[53] ^ data_in[54] ^ data_in[57] ^ data_in[63];
endmodule // oh_crc32_64b
/*
Copyright (c) 2014-2016 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/

81
common/hdl/oh_crc32_8b.v
View File

@ -1,81 +0,0 @@
/*
* CRC module eth_crc_8 (see license below)
*
* CRC width: 32
* Data width: 8
* CRC polynomial: 32'h4c11db7
* Configuration: galois
* Bit-reverse: input and output
*
* x^32 + x^26 + x^23 + x^22 + x^16 + x^12 + x^11 + x^10 + x^8 + x^7 + x^5 + x^4 + x^2 + x + 1
*
* Generated by https://github.com/alexforencich/fpga-utils/blob/master/crcgen.py/crcgen.py
*
* crcgen.py -b -r -d 8 -n eth_crc_8
*
*/
module oh_crc32_8b(/*AUTOARG*/
// Outputs
crc_next,
// Inputs
data_in, crc_state
);
input [7:0] data_in; // input data
input [31:0] crc_state; // old crc state
output [31:0] crc_next; // new crc state to store
assign crc_next[0] = crc_state[2] ^ crc_state[8] ^ data_in[2];
assign crc_next[1] = crc_state[0] ^ crc_state[3] ^ crc_state[9] ^ data_in[0] ^ data_in[3];
assign crc_next[2] = crc_state[0] ^ crc_state[1] ^ crc_state[4] ^ crc_state[10] ^ data_in[0] ^ data_in[1] ^ data_in[4];
assign crc_next[3] = crc_state[1] ^ crc_state[2] ^ crc_state[5] ^ crc_state[11] ^ data_in[1] ^ data_in[2] ^ data_in[5];
assign crc_next[4] = crc_state[0] ^ crc_state[2] ^ crc_state[3] ^ crc_state[6] ^ crc_state[12] ^ data_in[0] ^ data_in[2] ^ data_in[3] ^ data_in[6];
assign crc_next[5] = crc_state[1] ^ crc_state[3] ^ crc_state[4] ^ crc_state[7] ^ crc_state[13] ^ data_in[1] ^ data_in[3] ^ data_in[4] ^ data_in[7];
assign crc_next[6] = crc_state[4] ^ crc_state[5] ^ crc_state[14] ^ data_in[4] ^ data_in[5];
assign crc_next[7] = crc_state[0] ^ crc_state[5] ^ crc_state[6] ^ crc_state[15] ^ data_in[0] ^ data_in[5] ^ data_in[6];
assign crc_next[8] = crc_state[1] ^ crc_state[6] ^ crc_state[7] ^ crc_state[16] ^ data_in[1] ^ data_in[6] ^ data_in[7];
assign crc_next[9] = crc_state[7] ^ crc_state[17] ^ data_in[7];
assign crc_next[10] = crc_state[2] ^ crc_state[18] ^ data_in[2];
assign crc_next[11] = crc_state[3] ^ crc_state[19] ^ data_in[3];
assign crc_next[12] = crc_state[0] ^ crc_state[4] ^ crc_state[20] ^ data_in[0] ^ data_in[4];
assign crc_next[13] = crc_state[0] ^ crc_state[1] ^ crc_state[5] ^ crc_state[21] ^ data_in[0] ^ data_in[1] ^ data_in[5];
assign crc_next[14] = crc_state[1] ^ crc_state[2] ^ crc_state[6] ^ crc_state[22] ^ data_in[1] ^ data_in[2] ^ data_in[6];
assign crc_next[15] = crc_state[2] ^ crc_state[3] ^ crc_state[7] ^ crc_state[23] ^ data_in[2] ^ data_in[3] ^ data_in[7];
assign crc_next[16] = crc_state[0] ^ crc_state[2] ^ crc_state[3] ^ crc_state[4] ^ crc_state[24] ^ data_in[0] ^ data_in[2] ^ data_in[3] ^ data_in[4];
assign crc_next[17] = crc_state[0] ^ crc_state[1] ^ crc_state[3] ^ crc_state[4] ^ crc_state[5] ^ crc_state[25] ^ data_in[0] ^ data_in[1] ^ data_in[3] ^ data_in[4] ^ data_in[5];
assign crc_next[18] = crc_state[0] ^ crc_state[1] ^ crc_state[2] ^ crc_state[4] ^ crc_state[5] ^ crc_state[6] ^ crc_state[26] ^ data_in[0] ^ data_in[1] ^ data_in[2] ^ data_in[4] ^ data_in[5] ^ data_in[6];
assign crc_next[19] = crc_state[1] ^ crc_state[2] ^ crc_state[3] ^ crc_state[5] ^ crc_state[6] ^ crc_state[7] ^ crc_state[27] ^ data_in[1] ^ data_in[2] ^ data_in[3] ^ data_in[5] ^ data_in[6] ^ data_in[7];
assign crc_next[20] = crc_state[3] ^ crc_state[4] ^ crc_state[6] ^ crc_state[7] ^ crc_state[28] ^ data_in[3] ^ data_in[4] ^ data_in[6] ^ data_in[7];
assign crc_next[21] = crc_state[2] ^ crc_state[4] ^ crc_state[5] ^ crc_state[7] ^ crc_state[29] ^ data_in[2] ^ data_in[4] ^ data_in[5] ^ data_in[7];
assign crc_next[22] = crc_state[2] ^ crc_state[3] ^ crc_state[5] ^ crc_state[6] ^ crc_state[30] ^ data_in[2] ^ data_in[3] ^ data_in[5] ^ data_in[6];
assign crc_next[23] = crc_state[3] ^ crc_state[4] ^ crc_state[6] ^ crc_state[7] ^ crc_state[31] ^ data_in[3] ^ data_in[4] ^ data_in[6] ^ data_in[7];
assign crc_next[24] = crc_state[0] ^ crc_state[2] ^ crc_state[4] ^ crc_state[5] ^ crc_state[7] ^ data_in[0] ^ data_in[2] ^ data_in[4] ^ data_in[5] ^ data_in[7];
assign crc_next[25] = crc_state[0] ^ crc_state[1] ^ crc_state[2] ^ crc_state[3] ^ crc_state[5] ^ crc_state[6] ^ data_in[0] ^ data_in[1] ^ data_in[2] ^ data_in[3] ^ data_in[5] ^ data_in[6];
assign crc_next[26] = crc_state[0] ^ crc_state[1] ^ crc_state[2] ^ crc_state[3] ^ crc_state[4] ^ crc_state[6] ^ crc_state[7] ^ data_in[0] ^ data_in[1] ^ data_in[2] ^ data_in[3] ^ data_in[4] ^ data_in[6] ^ data_in[7];
assign crc_next[27] = crc_state[1] ^ crc_state[3] ^ crc_state[4] ^ crc_state[5] ^ crc_state[7] ^ data_in[1] ^ data_in[3] ^ data_in[4] ^ data_in[5] ^ data_in[7];
assign crc_next[28] = crc_state[0] ^ crc_state[4] ^ crc_state[5] ^ crc_state[6] ^ data_in[0] ^ data_in[4] ^ data_in[5] ^ data_in[6];
assign crc_next[29] = crc_state[0] ^ crc_state[1] ^ crc_state[5] ^ crc_state[6] ^ crc_state[7] ^ data_in[0] ^ data_in[1] ^ data_in[5] ^ data_in[6] ^ data_in[7];
assign crc_next[30] = crc_state[0] ^ crc_state[1] ^ crc_state[6] ^ crc_state[7] ^ data_in[0] ^ data_in[1] ^ data_in[6] ^ data_in[7];
assign crc_next[31] = crc_state[1] ^ crc_state[7] ^ data_in[1] ^ data_in[7];
endmodule // eth_crc_8
/*
Copyright (c) 2014-2016 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/

61
common/hdl/oh_debouncer.v
View File

@ -2,69 +2,68 @@
//# Function: A digital debouncer circuit #
//#############################################################################
//# Author: Andreas Olofsson #
//# License: MIT (see LICENSE file in OH! repository) #
//# License: MIT (see LICENSE file in OH! repository) #
//#############################################################################
module oh_debouncer #( parameter BOUNCE = 100, // bounce time (s)
parameter CLKPERIOD = 0.00001 // period (10ns=0.0001ms)
)
module oh_debouncer
#( parameter BOUNCE = 100, // bounce time (s)
parameter FREQUENCY = 1000000 // clock frequency (1Mhz)
)
(
input clk, // clock to synchronize to
input nreset, // syncronous active high reset
input noisy_in, // noisy input signal to filter
output clean_out // clean signal to logic
);
//################################
//# wires/regs/ params
//################################
parameter integer CW = $clog2(BOUNCE/CLKPERIOD);// counter width needed
parameter integer CW = $clog2(BOUNCE*FREQUENCY);
//regs
reg noisy_reg;
reg clean_out;
reg clean_reg;
// synchronize incoming signal
oh_dsync dsync (.dout (noisy_synced),
.clk (clk),
.nreset (nreset),
.din (noisy_in));
// synchronize reset to clk
oh_rsync rsync (.nrst_out (nreset_synced),
.clk (clk),
.nrst_in (nreset));
// detecting change in state on input
always @ (posedge clk or negedge nreset)
always @ (posedge clk or negedge nreset)
if(!nreset)
noisy_reg <= 1'b0;
noisy_reg <= 1'b0;
else
noisy_reg <= noisy_synced;
assign change_detected = noisy_reg ^ noisy_synced;
// synchronous counter "filter"
oh_counter #(.DW(CW))
oh_counter #(.DW(CW))
oh_counter (// Outputs
.count (),
.carry (carry),
.zero (),
.count (),
.wraparound (wraparound),
// Inputs
.clk (clk),
.in (1'b1),
.en (~carry), //done if you reach carry
.load (change_detected | ~nreset_synced),
.load_data ({(CW){1'b0}})
.clk (clk),
.in (1'b1),
.dir (1'b0),//increment
.en (1'b1),
.autowrap (1'b0),
.load (change_detected | ~nreset_synced),
.load_data ({(CW){1'b0}})
);
// sample noisy signal safely
always @ (posedge clk or negedge nreset)
if(!nreset)
clean_out <= 'b0;
else if(carry)
clean_out <= noisy_reg;
clean_reg <= 'b0;
else if(wraparound)
clean_reg <= noisy_reg;
assign clean_out = clean_reg;
endmodule // oh_debouncer

52
common/hdl/oh_dsync.v
View File

@ -2,36 +2,40 @@
//# Function: Clock synchronizer #
//#############################################################################
//# Author: Andreas Olofsson #
//# License: MIT (see LICENSE file in OH! repository) #
//# License: MIT (see LICENSE file in OH! repository) #
//#############################################################################
module oh_dsync #(parameter PS = 2, // number of sync stages
parameter DELAY = 0 // random delay
)
module oh_dsync
#(parameter PS = 2, // number of sync stages
parameter DELAY = 0, // random delay
parameter TYPE = "soft" // hard=hard macro,soft=synthesizable
)
(
input clk, // clock
input nreset, // clock
input din, // input data
output dout // synchronized data
);
`ifdef CFG_ASIC
asic_dsync asic_dsync (.clk(clk),
.nreset(nreset),
.din(din),
.dout(dout));
`else
reg [PS:0] sync_pipe;
always @ (posedge clk or negedge nreset)
if(!nreset)
sync_pipe[PS:0] <= 'b0;
else
sync_pipe[PS:0] <= {sync_pipe[PS-1:0],din};
// drive randomize delay from testbench
assign dout = (DELAY & sync_pipe[PS]) | //extra cycle
(~DELAY & sync_pipe[PS-1]); //default
`endif // !`ifdef CFG_ASIC
generate
if(TYPE=="soft")
begin
reg [PS:0] sync_pipe;
always @ (posedge clk or negedge nreset)
if(!nreset)
sync_pipe[PS:0] <= 'b0;
else
sync_pipe[PS:0] <= {sync_pipe[PS-1:0],din};
// drive randomize delay from testbench
assign dout = (DELAY & sync_pipe[PS]) | //extra cycle
(~DELAY & sync_pipe[PS-1]); //default
end // block: reg
else
begin
asic_dsync asic_dsync (.clk(clk),
.nreset(nreset),
.din(din),
.dout(dout));
end
endgenerate
endmodule // oh_dsync

247
common/hdl/oh_fifo_async.v
View File

@ -1,79 +1,200 @@
//#############################################################################
//# Function: Parametrized asynchronous clock FIFO #
//#############################################################################
// Notes: #
// Soft reference implementation always instantiated #
// Assumed to be optimized away in synthesis if needed #
//# Author: Andreas Olofsson #
//# License: MIT (see LICENSE file in OH! repository) #
//# License: MIT (see LICENSE file in OH! repository) #
//#############################################################################
module oh_fifo_async # (parameter DW = 104, // FIFO width
parameter DEPTH = 32, // FIFO depth (entries)
parameter TARGET = "GENERIC",// XILINX,ALTERA,GENERIC,ASIC
parameter PROG_FULL = (DEPTH/2),// program full threshold
parameter AW = $clog2(DEPTH) // binary read count width
)
module oh_fifo_async
#(parameter DW = 104, // FIFO width
parameter DEPTH = 32, // FIFO depth
parameter REG = 1, // Register fifo output
parameter AW = $clog2(DEPTH),// rd_count width (derived)
parameter PROGFULL = DEPTH-1, // programmable almost full level
parameter TYPE = "soft", // hard=name,soft=synthesizable
parameter CONFIG = "default", // hard macro user config pass through
parameter SHAPE = "square" // hard macro shape (square, tall, wide)
)
(
input nreset, // async reset
//Write Side
input wr_clk, // write clock
input wr_en, // write fifo
input [DW-1:0] din, // data to write
//Read Side
input rd_clk, // read clock
input rd_en, // read fifo
output [DW-1:0] dout, // output data (next cycle)
//Status
output full, // fifo is full
output prog_full, // fifo reaches full threshold
output empty, // fifo is empty
output [AW-1:0] rd_count // # of valid entries in fifo
//basic interface
input rdclk, // read side clock
input wrclk, // write side clock
input nreset, //async reset
input clear, //clear fifo (synchronous)
//write port
input write, // write fifo
input [DW-1:0] din, // data to write
output full, // fifo full
output progfull, //programmable full level
//read port
input read, // read fifo
output [DW-1:0] dout, // output data (next cycle)
output empty, // fifo is empty
output reg [AW-1:0] rdcount, // valid entries in fifo
// BIST interface
input bist_en, // bist enable
input bist_we, // write enable global signal
input [DW-1:0] bist_wem, // write enable vector
input [AW-1:0] bist_addr, // address
input [DW-1:0] bist_din, // data input
input [DW-1:0] bist_dout, // data input
// Power/repair (hard macro only)
input shutdown, // shutdown signal
input vss, // ground signal
input vdd, // memory array power
input vddio, // periphery/io power
input [7:0] memconfig, // generic memory config
input [7:0] memrepair // repair vector
);
//local wires
//local wires and registers
wire [AW-1:0] wr_count; // valid entries in fifo
reg [AW:0] wr_addr; // extra bit for wraparound comparison
reg [AW:0] wr_addr_ahead; // extra bit for wraparound comparison
reg [AW:0] rd_addr;
//#####################################
//# Select between hard and soft logic
//#####################################
generate
if (TARGET=="XILINX") begin : xilinx
if((DW==104) & (DEPTH==32))
begin : g104x32
fifo_async_104x32
fifo (
// Outputs
.full (full),
.prog_full (prog_full),
.dout (dout[DW-1:0]),
.empty (empty),
.rd_data_count (rd_count[AW-1:0]),
// Inputs
.rst (~nreset),
.wr_clk (wr_clk),
.rd_clk (rd_clk),
.wr_en (wr_en),
.din (din[DW-1:0]),
.rd_en (rd_en));
end // if ((DW==104) & (DEPTH==32))
if(TYPE=="soft") begin: gen_soft
assign dout[DW-1:0] = soft_dout[DW-1:0];
assign dout[DW-1:0] = soft_dout[DW-1:0]
endgenerate
//###########################
//# Full/empty indicators
//###########################
// uses one extra bit for compare to track wraparound pointers
// careful clock synchronization done using gray codes
// could get rid of gray2bin for rd_addr_sync...
// fifo indicators
assign soft_empty = (rd_addr_gray[AW:0] == wr_addr_gray_sync[AW:0]);
// fifo full
assign soft_full = (wr_addr[AW-1:0] == rd_addr_sync[AW-1:0]) &
(wr_addr[AW] != rd_addr_sync[AW]);
// programmable full
assign soft_progfull = (wr_addr_ahead[AW-1:0] == rd_addr_sync[AW-1:0]) &
(wr_addr_ahead[AW] != rd_addr_sync[AW]);
//###########################
//# Reset synchronizers
//###########################
oh_rsync wr_rsync (.nrst_out (wr_nreset),
.clk (wrclk),
.nrst_in (nreset));
oh_rsync rd_rsync (.nrst_out (rd_nreset),
.clk (rdclk),
.nrst_in (nreset));
//###########################
//# Write side address counter
//###########################
always @ ( posedge wr_clk or negedge wr_nreset)
if(!wr_nreset)
wr_addr[AW:0] <= 'b0;
else if(wr_en)
wr_addr[AW:0] <= wr_addr[AW:0] + 'd1;
//address lookahead for prog_full indicator
always @ (posedge wr_clk or negedge wr_nreset)
if(!wr_nreset)
wr_addr_ahead[AW:0] <= 'b0;
else if(~prog_full)
wr_addr_ahead[AW:0] <= wr_addr[AW:0] + PROG_FULL;
//###########################
//# Synchronize to read clk
//###########################
// convert to gray code (only one bit can toggle)
oh_bin2gray #(.DW(AW+1))
wr_b2g (.out (wr_addr_gray[AW:0]),
.in (wr_addr[AW:0]));
// synchronize to read clock
oh_dsync wr_sync[AW:0] (.dout (wr_addr_gray_sync[AW:0]),
.clk (rdclk),
.nreset(rd_nreset),
.din (wr_addr_gray[AW:0]));
//###########################
//#read side address counter
//###########################
always @ ( posedge rd_clk or negedge rd_nreset)
if(!rd_nreset)
rd_addr[AW:0] <= 'd0;
else if(read)
rd_addr[AW:0] <= rd_addr[AW:0] + 'd1;
//###########################
//# Synchronize to write clk
//###########################
//covert to gray (can't have multiple bits toggling)
oh_bin2gray #(.DW(AW+1))
rd_b2g (.out (rd_addr_gray[AW:0]),
.in (rd_addr[AW:0]));
//synchronize to wr clock
oh_dsync rd_sync[AW:0] (.dout (rd_addr_gray_sync[AW:0]),
.clk (wrclk),
.nreset (wr_nreset),
.din (rd_addr_gray[AW:0]));
//convert back to binary (for ease of use, rd_count)
oh_gray2bin #(.DW(AW+1))
rd_g2b (.out (rd_addr_sync[AW:0]),
.in (rd_addr_gray_sync[AW:0]));
//###########################
//# Full/empty indicators
//###########################
// uses one extra bit for compare to track wraparound pointers
// careful clock synchronization done using gray codes
// could get rid of gray2bin for rd_addr_sync...
// fifo indicators
assign empty = (rd_addr_gray[AW:0] == wr_addr_gray_sync[AW:0]);
// fifo full
assign full = (wr_addr[AW-1:0] == rd_addr_sync[AW-1:0]) &
(wr_addr[AW] != rd_addr_sync[AW]);
// programmable full
assign prog_full = (wr_addr_ahead[AW-1:0] == rd_addr_sync[AW-1:0]) &
(wr_addr_ahead[AW] != rd_addr_sync[AW]);
//asiclib
end
else begin : generic
oh_fifo_generic #(.DEPTH(DEPTH),
.DW(DW))
fifo_generic (
// Outputs
.full (full),
.prog_full (prog_full),
.dout (dout[DW-1:0]),
.empty (empty),
.rd_count (rd_count[AW-1:0]),
.wr_count (wr_count[AW-1:0]),
// Inputs
.nreset (nreset),
.wr_clk (wr_clk),
.rd_clk (rd_clk),
.wr_en (wr_en),
.din (din[DW-1:0]),
.rd_en (rd_en));
end
else:
//asiclib
endgenerate
endmodule // oh_fifo_async
// Local Variables:
// verilog-library-directories:("." "../fpga/" "../dv")

47
common/hdl/oh_fifo_sync.v
View File

@ -22,14 +22,14 @@ module oh_fifo_sync
input clear, //clear fifo (synchronous)
//write port
input [DW-1:0] din, // data to write
input wr_en, // write fifo
input write, // write fifo
output full, // fifo full
output almost_full, //progfull level reached
output progfull, //programmable full level
//read port
input rd_en, // read fifo
input read, // read fifo
output [DW-1:0] dout, // output data (next cycle)
output empty, // fifo is empty
output reg [AW-1:0] rd_count, // valid entries in fifo
output reg [AW-1:0] count, // valid entries in fifo
// BIST interface
input bist_en, // bist enable
input bist_we, // write enable global signal
@ -56,12 +56,13 @@ module oh_fifo_sync
wire ptr_match;
wire fifo_empty;
//############################
//#########################################################
// FIFO Control
//############################
assign fifo_read = rd_en & ~empty;
assign fifo_write = wr_en & ~full;
assign almost_full = (rd_count[AW-1:0] == PROGFULL);
//#########################################################
assign fifo_read = read & ~empty;
assign fifo_write = write & ~full;
assign almost_full = (count[AW-1:0] == PROGFULL);
assign ptr_match = (wr_addr[AW-1:0] == rd_addr[AW-1:0]);
assign full = ptr_match & (wr_addr[AW]==!rd_addr[AW]);
assign fifo_empty = ptr_match & (wr_addr[AW]==rd_addr[AW]);
@ -71,13 +72,13 @@ module oh_fifo_sync
begin
wr_addr[AW:0] <= 'd0;
rd_addr[AW:0] <= 'b0;
rd_count[AW-1:0] <= 'b0;
count[AW-1:0] <= 'b0;
end
else if(clear)
begin
wr_addr[AW:0] <= 'd0;
rd_addr[AW:0] <= 'b0;
rd_count[AW-1:0] <= 'b0;
wr_addr[AW:0] <= 'd0;
rd_addr[AW:0] <= 'b0;
count[AW-1:0] <= 'b0;
end
else if(fifo_write & fifo_read)
begin
@ -86,13 +87,13 @@ module oh_fifo_sync
end
else if(fifo_write)
begin
wr_addr[AW:0] <= wr_addr[AW:0] + 'd1;
rd_count[AW-1:0]<= rd_count[AW-1:0] + 'd1;
wr_addr[AW:0] <= wr_addr[AW:0] + 'd1;
count[AW-1:0] <= count[AW-1:0] + 'd1;
end
else if(fifo_read)
begin
rd_addr[AW:0] <= rd_addr[AW:0] + 'd1;
rd_count[AW-1:0]<= rd_count[AW-1:0] - 'd1;
rd_addr[AW:0] <= rd_addr[AW:0] + 'd1;
count[AW-1:0] <= count[AW-1:0] - 'd1;
end
//Pipeline register to account for RAM output register
@ -102,6 +103,16 @@ module oh_fifo_sync
assign empty = (REG==1) ? empty_reg :
fifo_empty;
//############################
// Memory Array
//############################
generate
if(TYPE=="soft") begin: ram_soft
end
//############################
// Dual Ported Memory
//############################
@ -123,7 +134,7 @@ module oh_fifo_sync
.wr_en (fifo_write),
.wr_wem ({(DW){1'b1}}),
.wr_addr (wr_addr[AW-1:0]),
.wr_din (din[DW-1:0]),
.wr_din (wr_din[DW-1:0]),
/*AUTOINST*/
// Inputs
.bist_en (bist_en),

15
common/hdl/oh_iddr.v
View File

@ -2,11 +2,11 @@
//# Function: Dual data rate input buffer (2 cycle delay) #
//#############################################################################
//# Author: Andreas Olofsson #
//# License: MIT (see LICENSE file in OH! repository) #
//# License: MIT (see LICENSE file in OH! repository) #
//#############################################################################
module oh_iddr #(parameter DW = 1 // width of data inputs
)
module oh_iddr
#(parameter DW = 2) // width of data inputs
(
input clk, // clock
input ce0, // 1st cycle enable
@ -14,12 +14,12 @@ module oh_iddr #(parameter DW = 1 // width of data inputs
input [DW/2-1:0] din, // data input sampled on both edges of clock
output reg [DW-1:0] dout // iddr aligned
);
//regs("sl"=stable low, "sh"=stable high)
reg [DW/2-1:0] din_sl;
reg [DW/2-1:0] din_sh;
reg ce0_negedge;
//########################
// Pipeline valid for negedge
//########################
@ -44,8 +44,5 @@ module oh_iddr #(parameter DW = 1 // width of data inputs
if(ce1)
dout[DW-1:0] <= {din_sh[DW/2-1:0],
din_sl[DW/2-1:0]};
endmodule // oh_iddr

10
common/hdl/oh_lat0.v
View File

@ -2,11 +2,11 @@
//# Function: Latch data when clk=0 #
//#############################################################################
//# Author: Andreas Olofsson #
//# License: MIT (see LICENSE file in OH! repository) #
//# License: MIT (see LICENSE file in OH! repository) #
//#############################################################################
module oh_lat0 #(parameter DW = 1 // data width
)
)
( input clk, // clk, latch when clk=0
input [DW-1:0] in, // input data
output [DW-1:0] out // output data (stable/latched when clk=1)
@ -18,13 +18,11 @@ module oh_lat0 #(parameter DW = 1 // data width
.in(in[DW-1:0]),
.out(out[DW-1:0]));
`else
reg [DW-1:0] out_reg;
always_latch
reg [DW-1:0] out_reg;
always @ (clk or in)
if (!clk)
out_reg[DW-1:0] <= in[DW-1:0];
assign out[DW-1:0] = out_reg[DW-1:0];
`endif
endmodule // oh_lat0

10
common/hdl/oh_lat1.v
View File

@ -2,7 +2,7 @@
//# Function: Achive high latch #
//#############################################################################
//# Author: Andreas Olofsson #
//# License: MIT (see LICENSE file in OH! repository) #
//# License: MIT (see LICENSE file in OH! repository) #
//#############################################################################
module oh_lat1 #(parameter DW = 1 //data width
@ -17,11 +17,11 @@ module oh_lat1 #(parameter DW = 1 //data width
.in(in[DW-1:0]),
.out(out[DW-1:0]));
`else
reg [DW-1:0] out_reg;
always_latch
reg [DW-1:0] out_reg;
always @ (clk or in)
if (clk)
out_reg[DW-1:0] <= in[DW-1:0];
assign out[DW-1:0] = out_reg[DW-1:0];
assign out[DW-1:0] = out_reg[DW-1:0];
`endif
endmodule // oh_lat1

2
common/hdl/oh_memory.v
View File

@ -82,7 +82,7 @@ module oh_memory
.DUALPORT(DUALPORT),
.CONFIG(CONFIG),
.SHAPE(SHAPE))
asic_ram(
ram(
// Outputs
.rd_dout (rd_dout[DW-1:0]),
// Inputs

60
common/hdl/oh_mux12.v
View File

@ -2,38 +2,39 @@
//# Function: 12:1 one hot mux #
//#############################################################################
//# Author: Andreas Olofsson #
//# License: MIT (see LICENSE file in OH! repository) #
//# License: MIT (see LICENSE file in OH! repository) #
//#############################################################################
module oh_mux12 #(parameter DW = 1 ) // width of mux
module oh_mux12
#(parameter DW = 1 ) // width of mux
(
input sel11,
input sel10,
input sel9,
input sel8,
input sel7,
input sel6,
input sel5,
input sel4,
input sel3,
input sel2,
input sel1,
input sel0,
input [DW-1:0] in11,
input [DW-1:0] in10,
input [DW-1:0] in9,
input [DW-1:0] in8,
input [DW-1:0] in7,
input [DW-1:0] in6,
input [DW-1:0] in5,
input [DW-1:0] in4,
input [DW-1:0] in3,
input [DW-1:0] in2,
input [DW-1:0] in1,
input [DW-1:0] in0,
output [DW-1:0] out //selected data output
input sel11,
input sel10,
input sel9,
input sel8,
input sel7,
input sel6,
input sel5,
input sel4,
input sel3,
input sel2,
input sel1,
input sel0,
input [DW-1:0] in11,
input [DW-1:0] in10,
input [DW-1:0] in9,
input [DW-1:0] in8,
input [DW-1:0] in7,
input [DW-1:0] in6,
input [DW-1:0] in5,
input [DW-1:0] in4,
input [DW-1:0] in3,
input [DW-1:0] in2,
input [DW-1:0] in1,
input [DW-1:0] in0,
output [DW-1:0] out //selected data output
);
assign out[DW-1:0] = ({(DW){sel0}} & in0[DW-1:0] |
{(DW){sel1}} & in1[DW-1:0] |
{(DW){sel2}} & in2[DW-1:0] |
@ -46,6 +47,5 @@ module oh_mux12 #(parameter DW = 1 ) // width of mux
{(DW){sel9}} & in9[DW-1:0] |
{(DW){sel10}} & in10[DW-1:0] |
{(DW){sel11}} & in11[DW-1:0]);
endmodule // oh_mux12
endmodule // oh_mux12

44
common/hdl/oh_ram.v
View File

@ -1,16 +1,16 @@
//#############################################################################
//# Function: Generic Memory #
//# Function: Generic Dual Port RAM #
//#############################################################################
//# Author: Andreas Olofsson #
//# License: MIT (see LICENSE file in OH! repository) #
//#############################################################################
module oh_ram # (parameter DW = 104, // memory width
parameter DEPTH = 32, // memory depth
parameter REG = 1, // register output
parameter DUALPORT= 1, // limit dual port
parameter AW = $clog2(DEPTH) // address width
)
module oh_ram_dp
# (parameter DW = 104, // memory width
parameter DEPTH = 32, // memory depth
parameter REG = 1, // register output
parameter AW = $clog2(DEPTH) // address width
)
(// read-port
input rd_clk,// rd clock
input rd_en, // memory access
@ -25,10 +25,10 @@ module oh_ram # (parameter DW = 104, // memory width
// BIST interface
input bist_en, // bist enable
input bist_we, // write enable global signal
input [DW-1:0] bist_wem, // write enable vector
input [AW-1:0] bist_addr, // address
input [DW-1:0] bist_din, // data input
input [DW-1:0] bist_dout, // data input
input [DW-1:0] bist_wem, // write enable vector
output [DW-1:0] bist_dout, // data output
// Power/repair (hard macro only)
input shutdown, // shutdown signal
input vss, // ground signal
@ -42,28 +42,30 @@ module oh_ram # (parameter DW = 104, // memory width
wire [DW-1:0] rdata;
wire [AW-1:0] dp_addr;
integer i;
//#########################################
//limiting dual port
//#########################################
assign dp_addr[AW-1:0] = (DUALPORT==1) ? rd_addr[AW-1:0] :
wr_addr[AW-1:0];
//#########################################
//write port
// bist mux
//#########################################
assign wr_we_mux = bist_en ? bist_we : wr_we;
assign wr_din_mux[DW-1:0] = bist_en ? bist_din[DW-1:0] : wr_din[DW-1:0];
assign wr_addr_mux[AW-1:0] = bist_en ? bist_addr[AW-1:0] : wr_addr[AW-1:0];
assign wr_wem_mux[DW-1:0] = bist_en ? bist_wem[DW-1:0] : wr_wem[DW-1:0];
//#########################################
// write port
//#########################################
always @(posedge wr_clk)
for (i=0;i<DW;i=i+1)
if (wr_en & wr_wem[i])
ram[wr_addr[AW-1:0]][i] <= wr_din[i];
if (wr_en_mux & wr_wem_mux[i])
ram[wr_addr_mux[AW-1:0]][i] <= wr_din_mux[i];
//#########################################
//read port
// read port
//#########################################
assign rdata[DW-1:0] = ram[dp_addr[AW-1:0]];
assign rdata[DW-1:0] = ram[rd_addr[AW-1:0]];
//Configurable output register
reg [DW-1:0] rd_reg;

57
common/hdl/oh_regfile.v
View File

@ -2,78 +2,75 @@
//# Function: Parametrized register file #
//#############################################################################
//# Author: Andreas Olofsson #
//# License: MIT (see LICENSE file in OH! repository) #
//# License: MIT (see LICENSE file in OH! repository) #
//#############################################################################
module oh_regfile # (parameter REGS = 32, // number of registeres
parameter RW = 64, // register width
parameter RP = 5, // read ports
parameter WP = 3, // write prots
parameter RAW = $clog2(REGS)// (derived) rf addr width
)
module oh_regfile
# (parameter REGS = 8, // number of registeres
parameter RW = 16, // register width
parameter RP = 5, // read ports
parameter WP = 3, // write prots
parameter RAW = $clog2(REGS)// (derived) rf addr width
)
(//Control inputs
input clk,
// Write Ports (concatenated)
input [WP-1:0] wr_valid, // write access
input [WP*RAW-1:0] wr_addr, // register address
input [WP*RW-1:0] wr_data, // write data
// Read Ports (concatenated)
// Read Ports (concatenated)
input [RP-1:0] rd_valid, // read access
input [RP*RAW-1:0] rd_addr, // register address
output [RP*RW-1:0] rd_data // output data
);
reg [RW-1:0] mem[0:REGS-1];
wire [WP-1:0] write_en [0:REGS-1];
wire [RW-1:0] datamux [0:REGS-1];
genvar i,j;
//TODO: Make an array of cells
//#########################################
// write ports
//#########################################
//#########################################
//One hote write enables
for(i=0;i<REGS;i=i+1)
for(i=0;i<REGS;i=i+1)
begin: gen_regwrite
for(j=0;j<WP;j=j+1)
begin: gen_wp
for(j=0;j<WP;j=j+1)
begin: gen_wp
assign write_en[i][j] = wr_valid[j] & (wr_addr[j*RAW+:RAW] == i);
end
end
//Multi Write-Port Mux
for(i=0;i<REGS;i=i+1)
for(i=0;i<REGS;i=i+1)
begin: gen_wrmux
oh_mux #(.DW(RW), .N(WP))
iwrmux(.out (datamux[i][RW-1:0]),
.sel (write_en[i][WP-1:0]),
.in (wr_data[WP*RW-1:0]));
end
//Memory Array Write
for(i=0;i<REGS;i=i+1)
for(i=0;i<REGS;i=i+1)
begin: gen_reg
always @ (posedge clk)
if (|write_en[i][WP-1:0])
mem[i] <= datamux[i];
end
//#########################################
// read ports
//#########################################
//#########################################
for (i=0;i<RP;i=i+1) begin: gen_rdport
assign rd_data[i*RW+:RW] = {(RW){rd_valid[i]}} &
assign rd_data[i*RW+:RW] = {(RW){rd_valid[i]}} &
mem[rd_addr[i*RAW+:RAW]];
end
endmodule // oh_regfile