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Adding reset hardware state machine
-concept developed by Gunnar Hillerstrom (VHDL) -takes the driver out of the picture -some people will run this bare metal -more deterministic -cuts down on hw/sw development issues
This commit is contained in:
Andreas Olofsson
parent
a094f835c9
commit
5c690d38a1
@ -1,5 +1,5 @@
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/*###########################################################################
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# Function: Clock generator for elink
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# Function: Clock and reset generator
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#
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# tx_lclk_div4 - Parallel data clock (125Mhz)
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#
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@ -15,36 +15,113 @@
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module eclocks (/*AUTOARG*/
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// Outputs
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tx_lclk, tx_lclk90, tx_lclk_div4, rx_lclk, rx_lclk_div4, cclk_p,
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cclk_n,
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tx_lclk, tx_lclk90, tx_lclk_div4, rx_lclk, rx_lclk_div4,
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rx_ref_clk, cclk_p, cclk_n, elink_reset, chip_resetb,
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// Inputs
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reset, clkin_elink, clkin_cclk
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hard_reset, elink_en, sys_clk, rx_lclk_pll
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);
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/****************************************************************/
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/*WARNING!! THIS CLOCK MUST MATCH THE ACTUAL INPUT CLOCK PERIOD!*/
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/****************************************************************/
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parameter ELINK_CLKIN_PERIOD = 3.3333333; // (2.5-100ns, set by system)
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parameter CCLK_CLKIN_PERIOD = 10; // (2.5-100ns, set by system)
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parameter RCW = 4; // reset counter width
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//Input clock, reset, config interface
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input reset; // hardware reset
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input clkin_elink; // clock input for elink PLL
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input clkin_cclk; // clock input for cclk PLL
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input hard_reset; // por_reset
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input elink_en; // elink enable (from pin or register)
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//Main input clocks
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input sys_clk; // clock for generating TX and CCLK
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input rx_lclk_pll; // RX clock directly from IO
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//TX Clocks
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output tx_lclk; // tx clock for DDR IO
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output tx_lclk90; // tx output clock shifted by 90 degrees
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output tx_lclk_div4; // tx slow clock for logic
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output tx_lclk; // tx clock for DDR IO
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output tx_lclk90; // tx output clock shifted by 90 degrees
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output tx_lclk_div4; // tx slow clock for logic
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//RX Clocks
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output rx_lclk; // rx high speed clock for DDR IO
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output rx_lclk_div4; // rx slow clock for logic
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output rx_lclk; // rx high speed clock for DDR IO
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output rx_lclk_div4; // rx slow clock for logic
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output rx_ref_clk; // clock for idelay element
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//Epiphany "free running" clock
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output cclk_p, cclk_n;
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//Reset
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output elink_reset; // reset for elink logic & IO
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output chip_resetb; // reset fpr Epiphany chip
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//###########################
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// RESET STATE MACHINE
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//###########################
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wire cclk_locked;
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wire lclk_locked;
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reg [RCW:0] reset_counter = 'b0; //works b/c of free running counter!
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reg heartbeat;
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reg reset_in;
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reg reset_sync;
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reg pll_locked_sync;
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reg pll_locked;
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wire pll_reset;
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reg [2:0] reset_state;
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//wrap around counter that generates a 1 cycle heartbeat
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//free running counter...
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always @ (posedge sys_clk)
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begin
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reset_counter[RCW-1:0] <= reset_counter[RCW-1:0]+1'b1;
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heartbeat <= ~(|reset_counter[RCW-1:0]);
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end
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//two clock synchronizer
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always @ (posedge sys_clk)
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begin
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pll_locked_sync <= cclk_locked & lclk_locked;
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reset_sync <= (hard_reset | ~elink_en);
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reset_in <= reset_sync;
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pll_locked <= pll_locked_sync;
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end
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`define RESET_ALL 3'b000
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`define START_PLL 3'b001
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`define STOP_PLL 3'b010
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`define START_EPIPHANY 3'b011
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`define HOLD_IT 3'b100
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`define ACTIVE 3'b101
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//Reset sequence state machine
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always @ (posedge sys_clk)
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if(reset_in)
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reset_state[2:0] <= `RESET_ALL;
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else if(heartbeat)
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case(reset_state[2:0])
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`RESET_ALL :
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reset_state[2:0] <= `START_PLL;
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`START_PLL :
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if(pll_locked)
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reset_state[2:0] <= `STOP_PLL;
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`STOP_PLL :
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reset_state[2:0] <= `START_EPIPHANY;
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`START_EPIPHANY :
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reset_state[2:0] <= `HOLD_IT;
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`HOLD_IT :
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if(pll_locked)
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reset_state[2:0] <= `ACTIVE;
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`ACTIVE:
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reset_state[2:0] <= `ACTIVE; //stay there until nex reset
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endcase // case (reset_state[2:0])
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//reset PLL during 'reset' and during quiet time around reset edge
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assign pll_reset = (reset_state[2:0]==`RESET_ALL) |
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(reset_state[2:0]==`STOP_PLL) |
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(reset_state[2:0]==`START_EPIPHANY);
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assign chip_resetb = (reset_state[2:0]==`START_EPIPHANY) |
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(reset_state[2:0]==`HOLD_IT) |
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(reset_state[2:0]==`ACTIVE);
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assign elink_reset = (reset_state[2:0]!=`ACTIVE);
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`ifdef TARGET_XILINX
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wire cclk_fb;
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@ -55,8 +132,9 @@ module eclocks (/*AUTOARG*/
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//###########################
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// MMCM/PLL FOR CCLK
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//###########################
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parameter CCLK_VCO_MULT = 12;
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parameter CCLK_DIVIDE = 2;
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parameter CCLK_VCO_MULT = 12;
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parameter CCLK_DIVIDE = 2;
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parameter CCLK_CLKIN_PERIOD = 10; // (2.5-100ns, set by system)
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MMCME2_ADV
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#(
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@ -99,10 +177,10 @@ module eclocks (/*AUTOARG*/
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.CLKOUT5(),
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.CLKOUT6(),
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.PWRDWN(1'b0),
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.RST(1'b0),
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.RST(pll_reset), //reset
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.CLKFBIN(cclk_fb),
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.CLKFBOUT(cclk_fb),
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.CLKIN1(clkin_cclk),
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.CLKFBOUT(cclk_fb), //feedback clock
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.CLKIN1(sys_clk), //input clock
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.CLKIN2(1'b0),
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.CLKINSEL(1'b1),
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.DADDR(7'b0),
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@ -112,7 +190,7 @@ module eclocks (/*AUTOARG*/
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.DWE(1'b0),
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.DRDY(),
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.DO(),
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.LOCKED(),
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.LOCKED(cclk_locked), //locked indicator
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.PSCLK(1'b0),
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.PSEN(1'b0),
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.PSDONE(),
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@ -127,18 +205,18 @@ module eclocks (/*AUTOARG*/
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);
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//###########################
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// PLL FOR ELIN
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// PLL FOR ELINK
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//###########################
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parameter LCLK_VCO_MULT = 5; //1500MHz
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parameter TXCLK_DIVIDE = 5; //500MHz
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parameter RXCLK_DIVIDE = 5; //300MHz
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parameter LCLK_VCO_MULT = 5; //1500MHz
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parameter TXCLK_DIVIDE = 5; //500MHz
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parameter RXCLK_DIVIDE = 5; //300MHz
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parameter LCLK_CLKIN_PERIOD = 3.3333333; // (2.5-100ns, set by system)
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PLLE2_ADV
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#(
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.BANDWIDTH("OPTIMIZED"),
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.CLKFBOUT_MULT(LCLK_VCO_MULT),
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.CLKFBOUT_PHASE(0.0),
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.CLKIN1_PERIOD(ELINK_CLKIN_PERIOD),
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.CLKIN1_PERIOD(LCLK_CLKIN_PERIOD),
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.CLKOUT0_DIVIDE(CCLK_DIVIDE), // cclk
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.CLKOUT1_DIVIDE(TXCLK_DIVIDE), // tx_lclk
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.CLKOUT2_DIVIDE(TXCLK_DIVIDE), // tx_lclk90
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@ -169,10 +247,10 @@ module eclocks (/*AUTOARG*/
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.CLKOUT4(rx_lclk),
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.CLKOUT5(rx_lclk_div4),
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.PWRDWN(1'b0),
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.RST(1'b0),
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.RST(pll_reset),
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.CLKFBIN(lclk_fb),
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.CLKFBOUT(lclk_fb),
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.CLKIN1(clkin_elink),
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.CLKIN1(rx_lclk_pll),
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.CLKIN2(1'b0),
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.CLKINSEL(1'b1),
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.DADDR(7'b0),
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@ -182,11 +260,8 @@ module eclocks (/*AUTOARG*/
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.DWE(1'b0),
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.DRDY(),
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.DO(),
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.LOCKED()
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.LOCKED(lclk_locked)
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);
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`endif // `ifdef TARGET_XILINX
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@ -269,6 +344,7 @@ endmodule // eclocks
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/*
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Copyright (C) 2014 Adapteva, Inc.
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Contributed by Andreas Olofsson <andreas@adapteva.com>
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Contributed by Gunnar Hillerstrom
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This program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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