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Fifo read bug

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-fifo should be read when it's not empty and there is no wait pushback
This commit is contained in:
Andreas Olofsson 2015-04-23 20:07:10 -04:00
parent c4c1edc10f
commit 5c8fb41849
1 changed files with 5 additions and 5 deletions
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10
elink/hdl/erx.v
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@ -70,7 +70,6 @@ module erx (/*AUTOARG*/
wire ecfg_rx_enable; // From ecfg_rx of ecfg_rx.v wire ecfg_rx_enable; // From ecfg_rx of ecfg_rx.v
wire ecfg_rx_mmu_enable; // From ecfg_rx of ecfg_rx.v wire ecfg_rx_mmu_enable; // From ecfg_rx of ecfg_rx.v
wire edma_access; // From edma of edma.v wire edma_access; // From edma of edma.v
wire edma_wait; // From erx_disty of erx_disty.v wire edma_wait; // From erx_disty of erx_disty.v
wire emmu_access; // From emmu of emmu.v wire emmu_access; // From emmu of emmu.v
wire [PW-1:0] emmu_packet; // From emmu of emmu.v wire [PW-1:0] emmu_packet; // From emmu of emmu.v
@ -136,7 +135,7 @@ module erx (/*AUTOARG*/
.rd_clk (@"(substring vl-cell-name 0 4)"_clk), .rd_clk (@"(substring vl-cell-name 0 4)"_clk),
.wr_clk (rx_lclk_div4), .wr_clk (rx_lclk_div4),
.wr_en (@"(substring vl-cell-name 0 4)"_fifo_access), .wr_en (@"(substring vl-cell-name 0 4)"_fifo_access),
.rd_en (~@"(substring vl-cell-name 0 4)"_wait), .rd_en (~@"(substring vl-cell-name 0 4)"_wait & @"(substring vl-cell-name 0 4)"_access),
.reset (reset), .reset (reset),
.din (@"(substring vl-cell-name 0 4)"_fifo_packet[PW-1:0]), .din (@"(substring vl-cell-name 0 4)"_fifo_packet[PW-1:0]),
); );
@ -158,7 +157,7 @@ module erx (/*AUTOARG*/
.rd_clk (rxrd_clk), // Templated .rd_clk (rxrd_clk), // Templated
.wr_en (rxrd_fifo_access), // Templated .wr_en (rxrd_fifo_access), // Templated
.din (rxrd_fifo_packet[PW-1:0]), // Templated .din (rxrd_fifo_packet[PW-1:0]), // Templated
.rd_en (~rxrd_wait)); // Templated .rd_en (~rxrd_wait & rxrd_access)); // Templated
assign rxwr_access=~rxwr_empty; assign rxwr_access=~rxwr_empty;
@ -176,7 +175,7 @@ module erx (/*AUTOARG*/
.rd_clk (rxwr_clk), // Templated .rd_clk (rxwr_clk), // Templated
.wr_en (rxwr_fifo_access), // Templated .wr_en (rxwr_fifo_access), // Templated
.din (rxwr_fifo_packet[PW-1:0]), // Templated .din (rxwr_fifo_packet[PW-1:0]), // Templated
.rd_en (~rxwr_wait)); // Templated .rd_en (~rxwr_wait & rxwr_access)); // Templated
assign rxrr_access=~rxrr_empty; assign rxrr_access=~rxrr_empty;
@ -194,7 +193,7 @@ module erx (/*AUTOARG*/
.rd_clk (rxrr_clk), // Templated .rd_clk (rxrr_clk), // Templated
.wr_en (rxrr_fifo_access), // Templated .wr_en (rxrr_fifo_access), // Templated
.din (rxrr_fifo_packet[PW-1:0]), // Templated .din (rxrr_fifo_packet[PW-1:0]), // Templated
.rd_en (~rxrr_wait)); // Templated .rd_en (~rxrr_wait & rxrr_access)); // Templated
/***********************************************************/ /***********************************************************/
@ -247,6 +246,7 @@ module erx (/*AUTOARG*/
.rxrr_fifo_packet(rxrr_fifo_packet[PW-1:0]), .rxrr_fifo_packet(rxrr_fifo_packet[PW-1:0]),
// Inputs // Inputs
.clk (rx_lclk_div4), // Templated .clk (rx_lclk_div4), // Templated
.reset (reset),
.mmu_en (ecfg_rx_mmu_enable), // Templated .mmu_en (ecfg_rx_mmu_enable), // Templated
.emmu_access (emmu_access), .emmu_access (emmu_access),
.emmu_packet (emmu_packet[PW-1:0]), .emmu_packet (emmu_packet[PW-1:0]),