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Merge branch 'master' of github.com:aolofsson/oh

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aolofsson 2021-09-23 09:58:21 -04:00
commit 5d4ad5b17b
3 changed files with 148 additions and 125 deletions
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54
padring/hdl/oh_padring.v
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@ -29,7 +29,10 @@ module oh_padring
parameter WE_VDDIO = 8, parameter WE_VDDIO = 8,
parameter WE_VSSIO = 8, parameter WE_VSSIO = 8,
parameter WE_VDD = 8, parameter WE_VDD = 8,
parameter WE_VSS = 8 parameter WE_VSS = 8,
parameter ENABLE_CUTS = 1,
parameter ENABLE_POC = 1,
parameter TECH_CFG_WIDTH = 16
) )
( (
//CONTINUOUS GROUND //CONTINUOUS GROUND
@ -45,6 +48,7 @@ module oh_padring
input [NO_GPIO*8-1:0] no_cfg, // config input [NO_GPIO*8-1:0] no_cfg, // config
input [NO_GPIO-1:0] no_ie, // input enable input [NO_GPIO-1:0] no_ie, // input enable
input [NO_GPIO-1:0] no_oen, // output enable (bar) input [NO_GPIO-1:0] no_oen, // output enable (bar)
input [NO_GPIO*TECH_CFG_WIDTH-1:0] no_tech_cfg,
//SOUTH //SOUTH
inout [SO_DOMAINS-1:0] so_vddio, inout [SO_DOMAINS-1:0] so_vddio,
inout [SO_DOMAINS-1:0] so_vssio, inout [SO_DOMAINS-1:0] so_vssio,
@ -54,6 +58,7 @@ module oh_padring
input [SO_GPIO*8-1:0] so_cfg, // config input [SO_GPIO*8-1:0] so_cfg, // config
input [SO_GPIO-1:0] so_ie, // input enable input [SO_GPIO-1:0] so_ie, // input enable
input [SO_GPIO-1:0] so_oen, // output enable (bar) input [SO_GPIO-1:0] so_oen, // output enable (bar)
input [SO_GPIO*TECH_CFG_WIDTH-1:0] so_tech_cfg,
//EAST //EAST
inout [EA_DOMAINS-1:0] ea_vddio, inout [EA_DOMAINS-1:0] ea_vddio,
inout [EA_DOMAINS-1:0] ea_vssio, inout [EA_DOMAINS-1:0] ea_vssio,
@ -63,6 +68,7 @@ module oh_padring
input [EA_GPIO*8-1:0] ea_cfg, // config input [EA_GPIO*8-1:0] ea_cfg, // config
input [EA_GPIO-1:0] ea_ie, // input enable input [EA_GPIO-1:0] ea_ie, // input enable
input [EA_GPIO-1:0] ea_oen, // output enable (bar) input [EA_GPIO-1:0] ea_oen, // output enable (bar)
input [EA_GPIO*TECH_CFG_WIDTH-1:0] ea_tech_cfg,
//WEST //WEST
inout [WE_DOMAINS-1:0] we_vddio, inout [WE_DOMAINS-1:0] we_vddio,
inout [WE_DOMAINS-1:0] we_vssio, inout [WE_DOMAINS-1:0] we_vssio,
@ -71,7 +77,8 @@ module oh_padring
input [WE_GPIO-1:0] we_dout, // data to pad input [WE_GPIO-1:0] we_dout, // data to pad
input [WE_GPIO*8-1:0] we_cfg, // config input [WE_GPIO*8-1:0] we_cfg, // config
input [WE_GPIO-1:0] we_ie, // input enable input [WE_GPIO-1:0] we_ie, // input enable
input [WE_GPIO-1:0] we_oen // output enable (bar) input [WE_GPIO-1:0] we_oen, // output enable (bar)
input [WE_GPIO*TECH_CFG_WIDTH-1:0] we_tech_cfg
); );
@ -97,9 +104,10 @@ module oh_padring
.NVSSIO(NO_VSSIO), .NVSSIO(NO_VSSIO),
.NVDD(NO_VDD), .NVDD(NO_VDD),
.NVSS(NO_VSS), .NVSS(NO_VSS),
.POC(1), .POC(ENABLE_POC),
.LEFTCUT(1), .LEFTCUT(ENABLE_CUT),
.RIGHTCUT(1)) .RIGHTCUT(ENABLE_CUT),
.TECH_CFG_WIDTH(TECH_CFG_WIDTH))
i0 (.vdd (vdd), i0 (.vdd (vdd),
.vss (vss), .vss (vss),
// Outputs // Outputs
@ -113,7 +121,8 @@ module oh_padring
.dout (no_dout[NO_GPIO-1:0]), .dout (no_dout[NO_GPIO-1:0]),
.oen (no_oen[NO_GPIO-1:0]), .oen (no_oen[NO_GPIO-1:0]),
.ie (no_ie[NO_GPIO-1:0]), .ie (no_ie[NO_GPIO-1:0]),
.cfg (no_cfg[NO_GPIO*8-1:0])); .cfg (no_cfg[NO_GPIO*8-1:0]),
.tech_cfg(no_tech_cfg));
end end
//############################# //#############################
@ -129,9 +138,10 @@ module oh_padring
.NVSSIO(SO_VSSIO), .NVSSIO(SO_VSSIO),
.NVDD(SO_VDD), .NVDD(SO_VDD),
.NVSS(SO_VSS), .NVSS(SO_VSS),
.POC(1), .POC(ENABLE_POC),
.LEFTCUT(1), .LEFTCUT(ENABLE_CUT),
.RIGHTCUT(1)) .RIGHTCUT(ENABLE_CUT),
.TECH_CFG_WIDTH(TECH_CFG_WIDTH))
i0 (.vdd (vdd), i0 (.vdd (vdd),
.vss (vss), .vss (vss),
// Outputs // Outputs
@ -145,7 +155,8 @@ module oh_padring
.dout (so_dout[SO_GPIO-1:0]), .dout (so_dout[SO_GPIO-1:0]),
.oen (so_oen[SO_GPIO-1:0]), .oen (so_oen[SO_GPIO-1:0]),
.ie (so_ie[SO_GPIO-1:0]), .ie (so_ie[SO_GPIO-1:0]),
.cfg (so_cfg[SO_GPIO*8-1:0])); .cfg (so_cfg[SO_GPIO*8-1:0]),
.tech_cfg(so_tech_cfg));
end end
@ -162,9 +173,10 @@ module oh_padring
.NVSSIO(EA_VSSIO), .NVSSIO(EA_VSSIO),
.NVDD(EA_VDD), .NVDD(EA_VDD),
.NVSS(EA_VSS), .NVSS(EA_VSS),
.POC(1), .POC(ENABLE_POC),
.LEFTCUT(1), .LEFTCUT(ENABLE_CUT),
.RIGHTCUT(1)) .RIGHTCUT(ENABLE_CUT),
.TECH_CFG_WIDTH(TECH_CFG_WIDTH))
i0 (.vdd (vdd), i0 (.vdd (vdd),
.vss (vss), .vss (vss),
// Outputs // Outputs
@ -178,7 +190,8 @@ module oh_padring
.dout (ea_dout[EA_GPIO-1:0]), .dout (ea_dout[EA_GPIO-1:0]),
.oen (ea_oen[EA_GPIO-1:0]), .oen (ea_oen[EA_GPIO-1:0]),
.ie (ea_ie[EA_GPIO-1:0]), .ie (ea_ie[EA_GPIO-1:0]),
.cfg (ea_cfg[EA_GPIO*8-1:0])); .cfg (ea_cfg[EA_GPIO*8-1:0]),
.tech_cfg(ea_tech_cfg));
end end
@ -195,9 +208,10 @@ module oh_padring
.NVSSIO(WE_VSSIO), .NVSSIO(WE_VSSIO),
.NVDD(WE_VDD), .NVDD(WE_VDD),
.NVSS(WE_VSS), .NVSS(WE_VSS),
.POC(1), .POC(ENABLE_POC),
.LEFTCUT(1), .LEFTCUT(ENABLE_CUT),
.RIGHTCUT(1)) .RIGHTCUT(ENABLE_CUT),
.TECH_CFG_WIDTH(TECH_CFG_WIDTH))
i0 (.vdd (vdd), i0 (.vdd (vdd),
.vss (vss), .vss (vss),
@ -212,13 +226,11 @@ module oh_padring
.dout (we_dout[WE_GPIO-1:0]), .dout (we_dout[WE_GPIO-1:0]),
.oen (we_oen[WE_GPIO-1:0]), .oen (we_oen[WE_GPIO-1:0]),
.ie (we_ie[WE_GPIO-1:0]), .ie (we_ie[WE_GPIO-1:0]),
.cfg (we_cfg[WE_GPIO*8-1:0])); .cfg (we_cfg[WE_GPIO*8-1:0]),
.tech_cfg(we_tech_cfg));
end end
endgenerate endgenerate
endmodule // oh_padring endmodule // oh_padring

7
padring/hdl/oh_pads_corner.v
View File

@ -12,5 +12,12 @@ module oh_pads_corner
inout vss // common ground inout vss // common ground
); );
asic_iocorner i0 (
.vddio,
.vssio,
.vdd,
.vss
);
endmodule // oh_pads_corner endmodule // oh_pads_corner

10
padring/hdl/oh_pads_domain.v
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@ -14,7 +14,8 @@ module oh_pads_domain
parameter NVSS = 8, // total core ground pads parameter NVSS = 8, // total core ground pads
parameter POC = 1, // 1 = place poc cell parameter POC = 1, // 1 = place poc cell
parameter LEFTCUT = 1, // 1 = place cut on left (seen from center) parameter LEFTCUT = 1, // 1 = place cut on left (seen from center)
parameter RIGHTCUT = 1 // 1 = place cut on right (seen from center parameter RIGHTCUT = 1, // 1 = place cut on right (seen from center
parameter TECH_CFG_WIDTH = 16
) )
(//pad (//pad
inout [NGPIO-1:0] pad, // pad inout [NGPIO-1:0] pad, // pad
@ -29,7 +30,8 @@ module oh_pads_domain
output [NGPIO-1:0] din, // data from pad output [NGPIO-1:0] din, // data from pad
input [NGPIO-1:0] oen, // output enable (bar) input [NGPIO-1:0] oen, // output enable (bar)
input [NGPIO-1:0] ie, // input enable input [NGPIO-1:0] ie, // input enable
input [NGPIO*8-1:0] cfg // io config input [NGPIO*8-1:0] cfg, // io config
input [NGPIO*TECH_CFG_WIDTH-1:0] tech_cfg // technology-specific config
); );
generate generate
@ -58,7 +60,9 @@ module oh_pads_domain
.vss (vss), .vss (vss),
.vddio (vddio), .vddio (vddio),
.vssio (vssio), .vssio (vssio),
.pad (pad[i])); .pad (pad[i]),
.tech_cfg(tech_cfg[i*TECH_CFG_WIDTH+:TECH_CFG_WIDTH]));
end end
//###################### //######################