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Merge branch 'master' of https://github.com/parallella/oh

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This commit is contained in:
Andreas Olofsson 2015-08-07 07:56:44 -04:00
commit 5e50d78c51
11 changed files with 221 additions and 99 deletions
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33
Makefile.in Normal file
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have_vivado := $(shell which vivado 1>/dev/null 2>/dev/null && echo yes)
top_srcdir := @top_srcdir@
top_builddir := @top_builddir@
export
.PHONY: builddeps all parallella-16-nohdmi clean
help:
@echo "TARGETS:"
@echo "all -- everything (TODO)"
@echo "parallella-z7020 -- Parallella Embedded (no HDMI)"
builddeps:
@if [ "x$(have_vivado)" != "xyes" ]; then echo vivado not in path; exit 1; fi
all: builddeps parallella-z7020
# TODO
parallella-z7020: builddeps
vivado -mode batch -source $(top_srcdir)/projects/parallella-z7020/system_project.tcl
# Temporary
package_axi_elink: builddeps
vivado -mode batch -source $(top_srcdir)/elink/scripts/xilinx/package_axi_elink.tcl
# Temporary
elink: builddeps
vivado -mode batch -source $(top_srcdir)/elink/scripts/xilinx/run.tcl
clean:
find . \( -name "vivado*.log" -or -name "vivado*.jou" \) -delete

11
README.md
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@ -3,3 +3,14 @@
Open Hardware (Pure and Simple) Open Hardware (Pure and Simple)
(work in progress...) (work in progress...)
## Building
```
git clone https://github.com/parallella/oh.git
cd oh
mkdir build
cd build
../configure
make elink
```

12
configure vendored Executable file
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#!/bin/bash
if ! which vivado 1>/dev/null; then
echo ERROR: Vivado not in PATH
echo 'Try "source /opt/Xilinx/Vivado/201X.X/settings.sh"'
exit 1
fi
top_srcdir=$(dirname $(readlink -f "$0"))
top_builddir=$(pwd)
sed "s|@top_srcdir@|${top_srcdir}|g;s|@top_builddir@|${top_builddir}|g" \
< $top_srcdir/Makefile.in > $top_builddir/Makefile

2
elink/README.md
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@ -464,6 +464,7 @@ FIELD | DESCRIPTION
[11:0] | Output address bits 31:20 [11:0] | Output address bits 31:20
[43:12] | Output address bits 63:32 (TBD) [43:12] | Output address bits 63:32 (TBD)
###ERX_MMU (0xE8000) ###ERX_MMU (0xE8000)
A table of N entries for translating incoming 12 bit address to a new value. Entries are aligned on 8 byte boundaries. A table of N entries for translating incoming 12 bit address to a new value. Entries are aligned on 8 byte boundaries.
@ -472,6 +473,7 @@ FIELD | DESCRIPTION
[11:0] | Output address bits 31:20 [11:0] | Output address bits 31:20
[43:12] | Output address bits 63:32 (TBD) [43:12] | Output address bits 63:32 (TBD)
###ERX_READBACK (0xDxxxx) ###ERX_READBACK (0xDxxxx)
Source address to specify for slave (host) read requests Source address to specify for slave (host) read requests

57
elink/scripts/xilinx/package_axi_elink.tcl
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@ -1,46 +1,29 @@
######################################################## set pwd [file dirname [info script]]
set oh_path "../.." source $pwd/../../../include/oh.tcl
# ???
set_msg_config -id {ip_flow 19-459} -suppress set_msg_config -id {ip_flow 19-459} -suppress
######################################################## oh::ip::create axi_elink $top_builddir/axi_elink
#create a project
set block axi_elink
create_project $block . -force
####################################################### set elink_src_files [list \
#add files "$top_srcdir/common/hdl" \
add_files -norecurse $oh_path/common/hdl "$top_srcdir/emesh/hdl" \
add_files -norecurse $oh_path/emesh/hdl "$top_srcdir/emmu/hdl/emmu.v" \
add_files -norecurse $oh_path/emmu/hdl/emmu.v "$top_srcdir/edma/hdl/edma.v" \
add_files -norecurse $oh_path/edma/hdl/edma.v "$top_srcdir/emailbox/hdl/emailbox.v" \
add_files -norecurse $oh_path/emailbox/hdl/emailbox.v "$top_srcdir/elink/hdl" ]
add_files -norecurse $oh_path/elink/hdl set elink_constr_files [list \
"$top_srcdir/elink/scripts/xilinx/elink_clocks.xdc" \
"$top_srcdir/elink/scripts/xilinx/elink_pins.xdc" \
"$top_srcdir/elink/scripts/xilinx/elink_timing.xdc" ]
set elink_ip_files [concat $elink_src_files $elink_constr_files]
####################################################### oh::ip::add_files axi_elink $elink_ip_files
#Package IP # Does not work / is it needed ?
ipx::package_project -root_dir . #oh::ip::add_constraints $elink_constr_files
####################################################### oh::ip::set_properties $top_builddir/axi_elink
#Vendor settings
set_property vendor {www.parallella.org} [ipx::current_core]
set_property library {user} [ipx::current_core]
set_property taxonomy {{/AXI_Infrastructure}} [ipx::current_core]
set_property vendor_display_name {OH!} [ipx::current_core]
set_property company_url {www.parallella.org} [ipx::current_core]
#######################################################
#Device Families Supported
set_property supported_families \
{
{virtex7} {Production} \
{kintex7} {Production} \
{artix7} {Production} \
{zynq} {Production}} \
[ipx::current_core]
#######################################################
#Save files
ipx::save_core [ipx::current_core] ipx::save_core [ipx::current_core]

11
elink/scripts/xilinx/read_constraints.tcl
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@ -1,5 +1,10 @@
set SRC /home/aolofsson/Work_all/oh set pwd [file dirname [info script]]
read_xdc $SRC/elink/syn/xilinx/elink_pins.xdc source $pwd/../../../include/oh.tcl
read_xdc $SRC/elink/syn/xilinx/elink_timing.xdc
read_xdc $pwd/elink_pins.xdc
read_xdc $pwd/elink_timing.xdc
# Do we need this?
#read_xdc $pwd/elink_clocks.xdc

5
elink/scripts/xilinx/read_ip.tcl
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@ -1,3 +1,6 @@
read_ip ../../../xilibs/ip/fifo_async_104x16.xci set pwd [file dirname [info script]]
source $pwd/../../../include/oh.tcl
read_ip $top_srcdir/xilibs/ip/fifo_async_104x16/fifo_async_104x16.xci
read_ip $top_srcdir/xilibs/ip/fifo_async_104x32/fifo_async_104x32.xci

86
elink/scripts/xilinx/read_verilog.tcl
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@ -1,54 +1,58 @@
set SRC /home/aolofsson/Work_all/oh set pwd [file dirname [info script]]
source $pwd/../../../include/oh.tcl
#ONLY FOR REFERENCE EXAMPLE #ONLY FOR REFERENCE EXAMPLE
read_verilog $SRC/elink/hdl/axi_elink.v read_verilog $top_srcdir/elink/hdl/axi_elink.v
#ELINK #ELINK
read_verilog $SRC/elink/hdl/elink_constants.v read_verilog $top_srcdir/elink/hdl/elink_constants.v
read_verilog $SRC/elink/hdl/elink_regmap.v read_verilog $top_srcdir/elink/hdl/elink_regmap.v
read_verilog $SRC/elink/hdl/elink.v read_verilog $top_srcdir/elink/hdl/elink.v
read_verilog $SRC/elink/hdl/eclocks.v read_verilog $top_srcdir/elink/hdl/eclocks.v
read_verilog $SRC/elink/hdl/ereset.v read_verilog $top_srcdir/elink/hdl/ereset.v
read_verilog $SRC/elink/hdl/ecfg_elink.v read_verilog $top_srcdir/elink/hdl/ecfg_elink.v
read_verilog $SRC/elink/hdl/ecfg_if.v read_verilog $top_srcdir/elink/hdl/ecfg_if.v
read_verilog $SRC/elink/hdl/erx.v read_verilog $top_srcdir/elink/hdl/erx.v
read_verilog $SRC/elink/hdl/erx_core.v read_verilog $top_srcdir/elink/hdl/erx_core.v
read_verilog $SRC/elink/hdl/erx_fifo.v read_verilog $top_srcdir/elink/hdl/erx_fifo.v
read_verilog $SRC/elink/hdl/erx_cfg.v read_verilog $top_srcdir/elink/hdl/erx_cfg.v
read_verilog $SRC/elink/hdl/erx_arbiter.v read_verilog $top_srcdir/elink/hdl/erx_arbiter.v
read_verilog $SRC/elink/hdl/erx_protocol.v read_verilog $top_srcdir/elink/hdl/erx_protocol.v
read_verilog $SRC/elink/hdl/erx_remap.v read_verilog $top_srcdir/elink/hdl/erx_remap.v
read_verilog $SRC/elink/hdl/erx_io.v read_verilog $top_srcdir/elink/hdl/erx_io.v
read_verilog $SRC/elink/hdl/etx.v read_verilog $top_srcdir/elink/hdl/etx.v
read_verilog $SRC/elink/hdl/etx_core.v read_verilog $top_srcdir/elink/hdl/etx_core.v
read_verilog $SRC/elink/hdl/etx_fifo.v read_verilog $top_srcdir/elink/hdl/etx_fifo.v
read_verilog $SRC/elink/hdl/etx_cfg.v read_verilog $top_srcdir/elink/hdl/etx_cfg.v
read_verilog $SRC/elink/hdl/etx_arbiter.v read_verilog $top_srcdir/elink/hdl/etx_arbiter.v
read_verilog $SRC/elink/hdl/etx_protocol.v read_verilog $top_srcdir/elink/hdl/etx_protocol.v
read_verilog $SRC/elink/hdl/etx_remap.v read_verilog $top_srcdir/elink/hdl/etx_remap.v
read_verilog $SRC/elink/hdl/etx_io.v read_verilog $top_srcdir/elink/hdl/etx_io.v
read_verilog $top_srcdir/elink/hdl/esaxi.v
read_verilog $top_srcdir/elink/hdl/emaxi.v
#COMMON #COMMON
read_verilog $SRC/common/hdl/toggle2pulse.v read_verilog $top_srcdir/common/hdl/toggle2pulse.v
read_verilog $SRC/common/hdl/synchronizer.v read_verilog $top_srcdir/common/hdl/synchronizer.v
read_verilog $SRC/common/hdl/pulse_stretcher.v read_verilog $top_srcdir/common/hdl/pulse_stretcher.v
read_verilog $SRC/common/hdl/clock_divider.v read_verilog $top_srcdir/common/hdl/clock_divider.v
read_verilog $SRC/common/hdl/arbiter_priority.v read_verilog $top_srcdir/common/hdl/arbiter_priority.v
#EMESH #EMESH
read_verilog $SRC/emesh/hdl/emesh2packet.v read_verilog $top_srcdir/emesh/hdl/emesh2packet.v
read_verilog $SRC/emesh/hdl/packet2emesh.v read_verilog $top_srcdir/emesh/hdl/packet2emesh.v
#MEMORY/FIFO #MEMORY/FIFO
read_verilog $SRC/memory/hdl/fifo_async.v read_verilog $top_srcdir/memory/hdl/fifo_async.v
read_verilog $SRC/memory/hdl/fifo_cdc.v read_verilog $top_srcdir/memory/hdl/fifo_sync.v
read_verilog $SRC/memory/hdl/memory_dp.v read_verilog $top_srcdir/memory/hdl/fifo_cdc.v
read_verilog $SRC/memory/hdl/memory_sp.v read_verilog $top_srcdir/memory/hdl/memory_dp.v
read_verilog $SRC/memory/hdl/fifo_full_block.v read_verilog $top_srcdir/memory/hdl/memory_sp.v
read_verilog $SRC/memory/hdl/fifo_empty_block.v read_verilog $top_srcdir/memory/hdl/fifo_full_block.v
read_verilog $top_srcdir/memory/hdl/fifo_empty_block.v
#MMU #MMU
read_verilog $SRC/emmu/hdl/emmu.v read_verilog $top_srcdir/emmu/hdl/emmu.v
read_verilog $SRC/emailbox/hdl/emailbox.v read_verilog $top_srcdir/emailbox/hdl/emailbox.v
read_verilog $SRC/edma/hdl/edma.v read_verilog $top_srcdir/edma/hdl/edma.v

20
elink/scripts/xilinx/run.tcl
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@ -1,17 +1,20 @@
set pwd [file dirname [info script]]
source $pwd/../../../include/oh.tcl
########################################################### ###########################################################
#STEP0: Define variables #STEP0: Define variables
set OUTDIR ./tmp set OUTDIR ./tmp
set PART xc7z010clg400-1 set PART xc7z010clg400-1
set TOP elink_example set TOP axi_elink
file mkdir $OUTDIR file mkdir $OUTDIR
########################################################### ###########################################################
#STEP1: Read sources, constraints, IP files #STEP1: Read sources, constraints, IP files
create_project -in_memory -part $PART -force my_project create_project -in_memory -part $PART -force my_project
source read_verilog.tcl source $pwd/read_verilog.tcl
source read_constraints.tcl source $pwd/read_constraints.tcl
source read_ip.tcl source $pwd/read_ip.tcl
########################################################### ###########################################################
#STEP2: SYNTHESIS #STEP2: SYNTHESIS
@ -79,12 +82,3 @@ write_verilog -force $OUTDIR/$TOP.v
write_xdc -no_fixed_only -force $OUTDIR/$TOP.xdc write_xdc -no_fixed_only -force $OUTDIR/$TOP.xdc
write_bitstream -force $OUTDIR/$TOP.bit write_bitstream -force $OUTDIR/$TOP.bit

63
include/oh.tcl Normal file
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set top_srcdir [file dirname [info script]]/..
set top_builddir $top_srcdir
# Alias, some scripts use this atm.
# TODO: Remove
set oh_path $top_srcdir
# TODO: Support building out of tree
if [info exists ::env(top_builddir)] {
set top_builddir $::env(top_builddir)
}
namespace eval oh {
namespace eval ip {
proc create {ip_name ip_dir} {
# ::create_project $ip_name $ip_dir -force
::create_project -in_memory
::update_ip_catalog
}
proc add_files {ip_name ip_files} {
set fileset [::get_filesets sources_1]
::add_files -fileset $fileset -norecurse -scan_for_includes $ip_files
::set_property "top" "$ip_name" $fileset
}
# TODO: Does not work. filegroup is empty
proc add_constraints {ip_constr_files {processing_order late}} {
# set filegroup [::ipx::get_file_groups xilinx_v*synthesis -of_objects [::ipx::current_core]]
# puts $filegroup
# set f [::ipx::add_file $ip_constr_files $filegroup]
# ::set_property -dict \
# [list \
# type xdc \
# library_name {} \
# processing_order $processing_order \
# ] \
# $f
}
proc set_properties {ip_dir} {
set c ::ipx::current_core
::ipx::package_project -root_dir $ip_dir
::set_property vendor {www.parallella.org} [$c]
::set_property library {user} [$c]
::set_property taxonomy {{/AXI_Infrastructure}} [$c]
::set_property vendor_display_name {OH!} [$c]
::set_property company_url {www.parallella.org} [$c]
::set_property supported_families \
{
{virtex7} {Production} \
{kintex7} {Production} \
{artix7} {Production} \
{zynq} {Production} \
} \
[$c]
}
}; # namespace ip
}; # namespace oh

16
projects/axi_elink/axi_elink_oh.tcl
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@ -32,7 +32,8 @@ update_ip_catalog -rebuild
# Set 'sources_1' fileset object # Set 'sources_1' fileset object
set obj [get_filesets sources_1] set obj [get_filesets sources_1]
set files [list \ set files [list \
"[file normalize "$oh_path/xilibs/ip/fifo_async_104x16.xci"]"\ "[file normalize "$oh_path/xilibs/ip/fifo_async_104x16/fifo_async_104x16.xci"]"\
"[file normalize "$oh_path/xilibs/ip/fifo_async_104x32/fifo_async_104x32.xci"]"\
"[file normalize "$oh_path/memory/hdl/fifo_async.v"]"\ "[file normalize "$oh_path/memory/hdl/fifo_async.v"]"\
"[file normalize "$oh_path/memory/hdl/memory_dp.v"]"\ "[file normalize "$oh_path/memory/hdl/memory_dp.v"]"\
"[file normalize "$oh_path/emesh/hdl/packet2emesh.v"]"\ "[file normalize "$oh_path/emesh/hdl/packet2emesh.v"]"\
@ -76,7 +77,7 @@ set files [list \
add_files -norecurse -fileset $obj $files add_files -norecurse -fileset $obj $files
# Set 'sources_1' fileset file properties for remote files # Set 'sources_1' fileset file properties for remote files
set file "$oh_path/xilibs/ip/fifo_async_104x16.xci" set file "$oh_path/xilibs/ip/fifo_async_104x16/fifo_async_104x16.xci"
set file [file normalize $file] set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
if { ![get_property "is_locked" $file_obj] } { if { ![get_property "is_locked" $file_obj] } {
@ -84,6 +85,17 @@ if { ![get_property "is_locked" $file_obj] } {
} }
set_property "used_in_implementation" "0" $file_obj set_property "used_in_implementation" "0" $file_obj
# Set 'sources_1' fileset file properties for remote files
set file "$oh_path/xilibs/ip/fifo_async_104x32/fifo_async_104x32.xci"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
if { ![get_property "is_locked" $file_obj] } {
set_property "synth_checkpoint_mode" "Singular" $file_obj
}
set_property "used_in_implementation" "0" $file_obj
set file "$oh_path/memory/hdl/fifo_async.v" set file "$oh_path/memory/hdl/fifo_async.v"
set file [file normalize $file] set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]