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Renaming enoc to emesh for consistency
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aolofsson
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commit
60fdcbd3e6
@ -1,12 +1,12 @@
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/*******************************************************************************
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* Function: ENOC Command Decoder
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* Author: Andreas Olofsson
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* Function: EMESH Command Decoder
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* Author: Andreas Olofsson
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* License: MIT (see LICENSE file in OH! repository)
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*
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* see ./enoc_pack.v
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*
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* see ./emesh_pack.v
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*
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******************************************************************************/
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module enoc_decode
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module emesh_decode
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(
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//Packet Command
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input [15:0] cmd_in,
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@ -26,15 +26,15 @@ module enoc_decode
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output [2:0] cmd_size,
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output [7:0] cmd_user
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);
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//############################################
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// Command Decode
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//############################################
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//Writes
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assign cmd_write = ~cmd_in[3];
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assign cmd_write = ~cmd_in[3];
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assign cmd_write_stop = cmd_in[3:0]==1001;
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//Reads/atomics
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assign cmd_read = cmd_in[3:0]==1000;
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assign cmd_atomic_cas = cmd_in[3:0]==1011;
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@ -48,8 +48,5 @@ module enoc_decode
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assign cmd_length[3:0] = cmd_in[7:4];
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assign cmd_size[2:0] = cmd_in[10:8];
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assign cmd_user[7:0] = cmd_in[15:8];
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endmodule // enoc_decode
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242
src/emesh/hdl/emesh_memory.v
Normal file
242
src/emesh/hdl/emesh_memory.v
Normal file
@ -0,0 +1,242 @@
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/*******************************************************************************
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* Function: SRAM with EMESH interface
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* Author: Andreas Olofsson
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* License: MIT (see LICENSE file in OH! repository)
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*
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******************************************************************************/
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module emesh_memory
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# (parameter AW = 32, // address width
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parameter PW = 104, // packet width
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parameter IDW = 12, // ID width
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parameter DEPTH = 65536, // memory depth
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parameter FILENAME = "log", // instance name
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parameter EN_WAIT = 0, // 0=disable random wait
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parameter EN_MON = 0, // 0=disable monitor
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parameter WAIT_MASK = 32'h0000000F // range limiter for wait signal
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)
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(// clk,reset
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input clk,
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input nreset,
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input [IDW-1:0] coreid,
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// incoming read/write
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input valid_in,
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input [PW-1:0] packet_in,
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output ready_out, //pushback
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// back to mesh (readback data)
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output reg valid_out,
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output [PW-1:0] packet_out,
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input ready_in //pushback
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);
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//derived parameters
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localparam DW = AW; //always the same
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parameter MAW = $clog2(DEPTH);
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//###############
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//# LOCAL WIRES
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//##############
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wire [MAW-1:0] addr;
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wire [63:0] din;
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wire [63:0] dout;
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wire en;
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wire mem_rd;
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reg [7:0] wen;
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reg write_out;
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reg [1:0] datamode_out;
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reg [4:0] ctrlmode_out;
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reg [AW-1:0] dstaddr_out;
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wire [AW-1:0] srcaddr_out;
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wire [AW-1:0] data_out;
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reg [2:0] align_addr;
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wire [DW-1:0] din_aligned;
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wire [63:0] dout_aligned;
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wire ready_random; //TODO: make random
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wire ready_all;
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/*AUTOWIRE*/
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// Beginning of automatic wires (for undeclared instantiated-module outputs)
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wire cmd_atomic_add; // From p2e of emesh_unpack.v
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wire cmd_atomic_and; // From p2e of emesh_unpack.v
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wire cmd_atomic_or; // From p2e of emesh_unpack.v
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wire cmd_atomic_xor; // From p2e of emesh_unpack.v
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wire cmd_cas; // From p2e of emesh_unpack.v
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wire [3:0] cmd_length; // From p2e of emesh_unpack.v
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wire [3:0] cmd_opcode; // From p2e of emesh_unpack.v
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wire cmd_read; // From p2e of emesh_unpack.v
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wire [2:0] cmd_size; // From p2e of emesh_unpack.v
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wire [7:0] cmd_user; // From p2e of emesh_unpack.v
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wire cmd_write; // From p2e of emesh_unpack.v
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wire cmd_write_stop; // From p2e of emesh_unpack.v
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wire [2*AW-1:0] data; // From p2e of emesh_unpack.v
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wire [AW-1:0] dstaddr; // From p2e of emesh_unpack.v
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wire [AW-1:0] srcaddr; // From p2e of emesh_unpack.v
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// End of automatics
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emesh_unpack #(.AW(AW),
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.PW(PW))
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p2e (/*AUTOINST*/
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// Outputs
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.cmd_write (cmd_write),
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.cmd_write_stop (cmd_write_stop),
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.cmd_read (cmd_read),
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.cmd_atomic_add (cmd_atomic_add),
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.cmd_atomic_and (cmd_atomic_and),
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.cmd_atomic_or (cmd_atomic_or),
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.cmd_atomic_xor (cmd_atomic_xor),
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.cmd_cas (cmd_cas),
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.cmd_opcode (cmd_opcode[3:0]),
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.cmd_length (cmd_length[3:0]),
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.cmd_size (cmd_size[2:0]),
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.cmd_user (cmd_user[7:0]),
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.dstaddr (dstaddr[AW-1:0]),
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.srcaddr (srcaddr[AW-1:0]),
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.data (data[2*AW-1:0]),
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// Inputs
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.packet_in (packet_in[PW-1:0]));
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// Ready/valid
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assign ready_all = (ready_random | ready_in);
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assign en = valid_in & ready_all;
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assign mem_rd = (valid_in & ~write_in & ready_all);
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//Pushback Circuit (pass through problems?)
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assign readt_out = ready_all;// & valid_in
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//Address-in (shifted by three bits, 64 bit wide memory)
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assign addr[MAW-1:0] = dstaddr[MAW+2:3];
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//Shift up
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assign din_aligned[31:0] = (cmd_size[2:0]==3'b000) ? {(4){data[7:0]}} :
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(cmd_size[2:0]==3'b001) ? {(2){data[15:0]}} :
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data_in[31:0];
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//Data-in (hardoded width)
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assign din[63:0] =(cmd_size[2:0]==3'b011) ? {srcaddr[31:0],din_aligned[31:0]}:
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{din_aligned[31:0],din_aligned[31:0]};
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//Write mask
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always@*
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casez({cmd_write, cmd_size[1:0],dstaddr[2:0]})
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//Byte
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6'b100000 : wen[7:0] = 8'b00000001;
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6'b100001 : wen[7:0] = 8'b00000010;
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6'b100010 : wen[7:0] = 8'b00000100;
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6'b100011 : wen[7:0] = 8'b00001000;
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6'b100100 : wen[7:0] = 8'b00010000;
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6'b100101 : wen[7:0] = 8'b00100000;
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6'b100110 : wen[7:0] = 8'b01000000;
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6'b100111 : wen[7:0] = 8'b10000000;
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//Short
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6'b10100? : wen[7:0] = 8'b00000011;
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6'b10101? : wen[7:0] = 8'b00001100;
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6'b10110? : wen[7:0] = 8'b00110000;
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6'b10111? : wen[7:0] = 8'b11000000;
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//Word
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6'b1100?? : wen[7:0] = 8'b00001111;
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6'b1101?? : wen[7:0] = 8'b11110000;
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//Double
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6'b111??? : wen[7:0] = 8'b11111111;
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default : wen[7:0] = 8'b00000000;
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endcase // casez ({write, datamode_in[1:0],addr_in[2:0]})
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//Single ported memory
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defparam mem.N=64;
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defparam mem.DEPTH=DEPTH;
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oh_memory_sp mem(
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// Inputs
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.clk (clk),
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.en (en),
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.we (cmd_write),
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.wem ({
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{(8){wen[7]}},
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{(8){wen[6]}},
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{(8){wen[5]}},
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{(8){wen[4]}},
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{(8){wen[3]}},
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{(8){wen[2]}},
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{(8){wen[1]}},
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{(8){wen[0]}}
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}
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),
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.addr (addr[MAW-1:0]),
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.din (din[63:0]),
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.dout (dout[63:0]),
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.vdd (1'b1),
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.vddio (1'b1),
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.memrepair(8'b0),
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.memconfig(8'b0),
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.bist_en (1'b0),
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.bist_we (1'b0),
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.bist_wem (64'b0),
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.bist_addr({(MAW){1'b0}}),
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.bist_din (64'b0)
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);
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//Outgoing transaction
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always @ (posedge clk or negedge nreset)
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if(!nreset)
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valid_out <=1'b0;
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else
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begin
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valid_out <= mem_rd;
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write_out <= 1'b1;
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align_addr[2:0] <= dstaddr[2:0];
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datamode_out[1:0] <= datamode[1:0];
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ctrlmode_out[4:0] <= ctrlmode[4:0];
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dstaddr_out[AW-1:0] <= srcaddr[AW-1:0];
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end
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//Data alignment for readback
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emesh_rdalign emesh_rdalign (// Outputs
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.data_out (dout_aligned[63:0]),
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// Inputs
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.datamode (datamode_out[1:0]),
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.addr (align_addr[2:0]),
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.data_in (dout[63:0]));
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assign srcaddr_out[AW-1:0] = (datamode_out[1:0]==2'b11) ? dout[63:32] : 32'b0;
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assign data_out[31:0] = dout_aligned[31:0];
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//Concatenate
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emesh_pack #(.AW(AW),
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.PW(PW))
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e2p (// Outputs
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.packet_out (packet_out[PW-1:0]),
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// Inputs
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.opcode_in (cmd_opcode[3:0]),
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.length_in (cmd_length[3:0]),
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.size_in (cmd_size[2:0]),
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.user_in (cmd_user[7:3]),
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.dstaddr_in (dstaddr[AW-1:0]),
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.srcaddr_in (srcaddr[AW-1:0]),
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.data_in (data[2*AW-1:0]));
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// Traffic monitor
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emesh_monitor #(.PW(PW),
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.FILENAME(FILENAME),
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.ENABLE(EN_MON))
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emesh_monitor (.dut_valid (valid_in & write_in),
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.dut_packet (packet_in[PW-1:0]),
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.ready_in (ready_random),
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.clk (clk),
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.nreset (nreset));
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//Random wait generator //TODO: make this a module
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oh_pulse oh_pulse(// Outputs
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.out (pulse),
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// Inputs
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.clk (clk),
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.nreset (nreset),
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.en (1'b1),
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.mask (WAIT_MASK));
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if(EN_MON)
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assign ready_random = pulse;
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else
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assign ready_random = 1'b1;
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endmodule // emesh_memory
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// Local Variables:
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// verilog-library-directories:("." "../dv" "../../stdlib/hdl/")
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// End:
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@ -8,7 +8,8 @@
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/* verilator lint_off STMTDLY */
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module emesh_monitor
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# (parameter PW = 104, // packet width
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parameter FILENAME = "UNDEFINED" // filename
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parameter FILENAME = "UNDEFINED", // filename
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parameter ENABLE = 0 // enable block
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)
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(
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//clock and reset
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@ -20,34 +21,46 @@ module emesh_monitor
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input ready_in
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);
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`ifdef DEBUG
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generate
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if(ENABLE)
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begin
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//core name for trace
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reg [31:0] ftrace;
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reg [255:0] tracefile;
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//core name for trace
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reg [31:0] ftrace;
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reg [255:0] tracefile;
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initial
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begin
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#10
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$sformat(tracefile,"%0s_%0h%s",FILENAME);
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ftrace = $fopen({tracefile}, "w");
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end
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//Dumps into
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initial
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begin
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//TODO: Figure out these delays
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#10
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//index should be core ID
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$sformat(tracefile,"%0s_%0h%s",FILENAME);
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ftrace = $fopen({tracefile}, "w");
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end
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always @ (posedge clk)
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if(nreset & dut_valid & ready_in)
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if (PW==112) begin: p112
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$fwrite(ftrace, "%h_%h_%h_%h\n",
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dut_packet[110:80],
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dut_packet[79:48],
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dut_packet[47:16],
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dut_packet[15:0]);
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end
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else if (PW==144) begin: p144
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$fwrite(ftrace, "%h_%h_%h_%h\n",
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dut_packet[143:112],
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dut_packet[111:48],
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dut_packet[47:16],
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dut_packet[15:0]);
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end
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else if (PW==208) begin: p208
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$fwrite(ftrace, "%h_%h_%h_%h_%h\n",
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dut_packet[207:144],
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dut_packet[143:112],
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dut_packet[111:48],
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dut_packet[47:16],
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dut_packet[15:0]);
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end
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always @ (posedge clk)
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if(nreset & dut_valid & ready_in)
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if (PW==112) begin: p112
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$fwrite(ftrace, "%h_%h_%h_%h\n",dut_packet[110:80],dut_packet[79:48],dut_packet[47:16],dut_packet[15:0]);
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end
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else if (PW==144) begin: p144
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$fwrite(ftrace, "%h_%h_%h_%h\n",dut_packet[143:112],dut_packet[111:48],dut_packet[47:16],dut_packet[15:0]);
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end
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else if (PW==208) begin: p208
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$fwrite(ftrace, "%h_%h_%h_%h_%h\n",dut_packet[207:144],dut_packet[143:112],dut_packet[111:48],dut_packet[47:16],dut_packet[15:0]);
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end
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`endif // `ifdef DEBUG
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end
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endgenerate
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endmodule // emesh_monitor
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@ -1,12 +1,12 @@
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/*******************************************************************************
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* Function: Memory Mapped Transaction --> Packet Converter
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* Author: Andreas Olofsson
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* Function: Memory Mapped Transaction --> Packet Converter
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* Author: Andreas Olofsson
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* License: MIT (see LICENSE file in OH! repository)
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*
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* Documentation:
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*
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*
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* The following table shows the field mapping for different AW's:
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*
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*
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* | Packet | AW16 | AW32 | AW64 | AW128 |
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* |---------|---------|----------|--------|---------|
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* | 15:0 | DA,CMD | CMD | CMD | CMD |
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@ -25,17 +25,17 @@
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* | 335:304 | **** | **** | **** | D5 |
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* | 367:336 | **** | **** | **** | D6 |
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* | 399:368 | **** | **** | **** | D7 |
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*
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*
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* The following list shows the widths supported for each AW
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*
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*
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* |Packet | AW16 | AW32 | AW64 | AW128 |
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* |---------------|-------|--------|--------|--------|
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* |minimum | 40 | 72+8 | 136+8 | 264+8 |
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* |double/atomics | -- | 104+8 | 200+8 | 392+8 |
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*
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*
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* The command field has the following options:
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*
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*
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*
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*
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* | Command[15:0] | 15:11 | 10:8 | 7:4 | 3:0 |
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* |-----------------|-----------|-----------|----------|------|
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* | WRITE-START | USER[7:3] | SIZE[2:0] | LEN[3:0] | 0000 |
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@ -55,7 +55,7 @@
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* | ATOMIC-AND | USER[7:3] | SIZE[2:0] | LEN[3:0] | 1101 |
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* | ATOMIC-OR | USER[7:3] | SIZE[2:0] | LEN[3:0] | 1110 |
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* | ATOMIC-XOR | USER[7:3] | SIZE[2:0] | LEN[3:0] | 1111 |
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*
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*
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* SIZE DECODE:
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* 000=8b
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* 001=16b
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@ -65,20 +65,20 @@
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* 101=256b
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* 110=512b
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* 111=1024b
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*
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*
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* LENGTH DECODE:
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* 0000=1 beat (single transaction)
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* 0001=2 beat
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* ...
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* 1111=16 beats
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*
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*
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* AW32/AW64/AW128 formats are compatible
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* AW16 format is a standalone format not compatible with any other
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* All transactions are LSB aligned
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* All transactions are LSB aligned
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* No return address for AW16 (point to point)
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*
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*
|
||||
******************************************************************************/
|
||||
module enoc_pack
|
||||
module emesh_pack
|
||||
#(parameter AW = 64,
|
||||
parameter PW = 144)
|
||||
(
|
||||
@ -94,19 +94,19 @@ module enoc_pack
|
||||
//Output packet
|
||||
output [PW-1:0] packet_out
|
||||
);
|
||||
|
||||
|
||||
//############################################
|
||||
// Command Field
|
||||
//############################################
|
||||
wire [15:0] cmd_out;
|
||||
|
||||
assign cmd_out[3:0] = opcode_in[3:0];
|
||||
assign cmd_out[3:0] = opcode_in[3:0];
|
||||
assign cmd_out[7:4] = length_in[3:0];
|
||||
assign cmd_out[10:8] = size_in[2:0];
|
||||
assign cmd_out[15:11] = user_in[7:3];
|
||||
|
||||
|
||||
//Decode (only write indicator needed)
|
||||
enoc_decode enoc_decode (//Inputs
|
||||
emesh_decode enoc_decode (//Inputs
|
||||
.cmd_in (cmd_out[15:0]),
|
||||
// Outputs
|
||||
.cmd_write (cmd_write),
|
||||
@ -121,7 +121,7 @@ module enoc_pack
|
||||
.cmd_length (),
|
||||
.cmd_size (),
|
||||
.cmd_user ());
|
||||
|
||||
|
||||
generate
|
||||
//############################
|
||||
// 16-Bit ("lite/apb like")
|
||||
@ -145,13 +145,13 @@ module enoc_pack
|
||||
if(PW==80) begin: p80
|
||||
assign packet_out[15:0] = cmd_out[15:0];
|
||||
assign packet_out[47:16] = dstaddr_in[31:0];
|
||||
assign packet_out[79:48] = cmd_write ? data_in[31:0] :
|
||||
assign packet_out[79:48] = cmd_write ? data_in[31:0] :
|
||||
srcaddr_in[31:0];
|
||||
end
|
||||
else if(PW==112) begin: p112
|
||||
assign packet_out[15:0] = cmd_out[15:0];
|
||||
assign packet_out[47:16] = dstaddr_in[31:0];
|
||||
assign packet_out[79:48] = cmd_write ? data_in[31:0] :
|
||||
assign packet_out[79:48] = cmd_write ? data_in[31:0] :
|
||||
srcaddr_in[31:0];
|
||||
assign packet_out[111:80] = data_in[63:32];
|
||||
end
|
||||
@ -167,14 +167,14 @@ module enoc_pack
|
||||
if(PW==144) begin: p144
|
||||
assign packet_out[15:0] = cmd_out[15:0];
|
||||
assign packet_out[47:16] = dstaddr_in[31:0];
|
||||
assign packet_out[111:48] = cmd_write ? data_in[63:0] :
|
||||
assign packet_out[111:48] = cmd_write ? data_in[63:0] :
|
||||
srcaddr_in[63:0];
|
||||
assign packet_out[143:112] = dstaddr_in[63:32];
|
||||
end
|
||||
else if(PW==208) begin: p208
|
||||
assign packet_out[15:0] = cmd_out[15:0];
|
||||
assign packet_out[47:16] = dstaddr_in[31:0];
|
||||
assign packet_out[111:48] = cmd_write ? data_in[63:0] :
|
||||
assign packet_out[111:48] = cmd_write ? data_in[63:0] :
|
||||
srcaddr_in[63:0];
|
||||
assign packet_out[143:112] = dstaddr_in[63:32];
|
||||
assign packet_out[207:144] = data_in[127:64];
|
||||
@ -191,20 +191,20 @@ module enoc_pack
|
||||
if(PW==272) begin: p272
|
||||
assign packet_out[15:0] = cmd_out[15:0];
|
||||
assign packet_out[47:16] = dstaddr_in[31:0];
|
||||
assign packet_out[111:48] = cmd_write ? data_in[63:0] :
|
||||
assign packet_out[111:48] = cmd_write ? data_in[63:0] :
|
||||
srcaddr_in[63:0];
|
||||
assign packet_out[143:112] = dstaddr_in[63:32];
|
||||
assign packet_out[207:144] = cmd_write ? data_in[127:64] :
|
||||
assign packet_out[207:144] = cmd_write ? data_in[127:64] :
|
||||
srcaddr_in[127:64];
|
||||
assign packet_out[271:208] = dstaddr_in[127:64];
|
||||
end
|
||||
else if(PW==400) begin: p400
|
||||
assign packet_out[15:0] = cmd_out[15:0];
|
||||
assign packet_out[47:16] = dstaddr_in[31:0];
|
||||
assign packet_out[111:48] = cmd_write ? data_in[63:0] :
|
||||
assign packet_out[111:48] = cmd_write ? data_in[63:0] :
|
||||
srcaddr_in[63:0];
|
||||
assign packet_out[143:112] = dstaddr_in[63:32];
|
||||
assign packet_out[207:144] = cmd_write ? data_in[127:64] :
|
||||
assign packet_out[207:144] = cmd_write ? data_in[127:64] :
|
||||
srcaddr_in[127:64];
|
||||
assign packet_out[271:208] = dstaddr_in[127:64];
|
||||
assign packet_out[399:272] = data_in[255:128];
|
||||
@ -214,6 +214,5 @@ module enoc_pack
|
||||
$display ("Combo not supported (PW=%ds AW==%ds)", PW,AW);
|
||||
end
|
||||
end // block: aw128
|
||||
endgenerate
|
||||
endmodule // emesh2packet
|
||||
|
||||
endgenerate
|
||||
endmodule // emesh_pack
|
||||
@ -1,15 +1,15 @@
|
||||
/*******************************************************************************
|
||||
* Function: Packet-->Memory Mapped Transaction Converter
|
||||
* Author: Andreas Olofsson
|
||||
* Function: Packet-->Memory Mapped Transaction Converter
|
||||
* Author: Andreas Olofsson
|
||||
* License: MIT (see LICENSE file in OH! repository)
|
||||
*
|
||||
* Documentation:
|
||||
*
|
||||
* see ./enoc_pack.v for packet formatting
|
||||
*
|
||||
*
|
||||
* see ./emesh_pack.v for packet formatting
|
||||
*
|
||||
******************************************************************************/
|
||||
module enoc_unpack
|
||||
#(parameter AW = 32, // address width
|
||||
module emesh_unpack
|
||||
#(parameter AW = 32, // address width
|
||||
parameter PW = 104) // packet width
|
||||
(
|
||||
//Input packet
|
||||
@ -42,21 +42,21 @@ module enoc_unpack
|
||||
// Command Decode
|
||||
//############################################
|
||||
|
||||
enoc_decode enoc_decode (//Input
|
||||
.cmd_in (cmd[15:0]),
|
||||
// Outputs
|
||||
.cmd_write (cmd_write),
|
||||
.cmd_write_stop (cmd_write_stop),
|
||||
.cmd_read (cmd_read),
|
||||
.cmd_cas (cmd_cas),
|
||||
.cmd_atomic_add (cmd_atomic_add),
|
||||
.cmd_atomic_and (cmd_atomic_and),
|
||||
.cmd_atomic_or (cmd_atomic_or),
|
||||
.cmd_atomic_xor (cmd_atomic_xor),
|
||||
.cmd_opcode (cmd_opcode[3:0]),
|
||||
.cmd_user (cmd_user[7:0]),
|
||||
.cmd_length (cmd_length[3:0]),
|
||||
.cmd_size (cmd_size[2:0]));
|
||||
emesh_decode emesh_decode (//Input
|
||||
.cmd_in (cmd[15:0]),
|
||||
// Outputs
|
||||
.cmd_write (cmd_write),
|
||||
.cmd_write_stop (cmd_write_stop),
|
||||
.cmd_read (cmd_read),
|
||||
.cmd_cas (cmd_cas),
|
||||
.cmd_atomic_add (cmd_atomic_add),
|
||||
.cmd_atomic_and (cmd_atomic_and),
|
||||
.cmd_atomic_or (cmd_atomic_or),
|
||||
.cmd_atomic_xor (cmd_atomic_xor),
|
||||
.cmd_opcode (cmd_opcode[3:0]),
|
||||
.cmd_user (cmd_user[7:0]),
|
||||
.cmd_length (cmd_length[3:0]),
|
||||
.cmd_size (cmd_size[2:0]));
|
||||
generate
|
||||
//######################
|
||||
// 16-Bit ("lite/apb like")
|
||||
@ -83,7 +83,7 @@ module enoc_unpack
|
||||
assign dstaddr[31:0] = packet_in[47:16];
|
||||
assign srcaddr[31:0] = packet_in[79:48];
|
||||
assign data[31:0] = packet_in[79:48];
|
||||
assign data[63:32] = 32'b0;
|
||||
assign data[63:32] = 32'b0;
|
||||
end
|
||||
else if(PW==112) begin: p112
|
||||
assign cmd[15:0] = packet_in[15:0];
|
||||
@ -106,7 +106,7 @@ module enoc_unpack
|
||||
assign srcaddr[63:0] = packet_in[111:48];
|
||||
assign data[127:0] = packet_in[111:48];
|
||||
assign dstaddr[63:32] = packet_in[143:112];
|
||||
assign data[127:64] = 64'b0;
|
||||
assign data[127:64] = 64'b0;
|
||||
end
|
||||
else if(PW==208) begin: p208
|
||||
assign cmd[15:0] = packet_in[15:0];
|
||||
@ -134,7 +134,7 @@ module enoc_unpack
|
||||
assign data[127:64] = packet_in[207:144];
|
||||
assign srcaddr[127:64] = packet_in[207:144];
|
||||
assign dstaddr[127:64] = packet_in[271:208];
|
||||
assign data[255:128] = 128'b0;
|
||||
assign data[255:128] = 128'b0;
|
||||
end
|
||||
else if(PW==400) begin: p400
|
||||
assign cmd[15:0] = packet_in[15:0];
|
||||
@ -152,10 +152,6 @@ module enoc_unpack
|
||||
$display ("Combo not supported (PW=%ds AW==%ds)", PW,AW);
|
||||
end
|
||||
end // block: aw128
|
||||
endgenerate
|
||||
endgenerate
|
||||
|
||||
endmodule // enoc_unpack
|
||||
|
||||
|
||||
|
||||
|
||||
@ -1,46 +0,0 @@
|
||||
/* verilator lint_off STMTDLY */
|
||||
module emesh_monitor(/*AUTOARG*/
|
||||
// Inputs
|
||||
clk, nreset, dut_access, dut_packet, ready_in, coreid
|
||||
);
|
||||
|
||||
parameter PW = 104;
|
||||
parameter IDW = 12;
|
||||
parameter INDEX = 0;
|
||||
parameter NAME = "not_declared";
|
||||
|
||||
//clock and reset
|
||||
input clk;
|
||||
input nreset;
|
||||
|
||||
//monitors transaction on the wire
|
||||
input dut_access;
|
||||
input [PW-1:0] dut_packet;
|
||||
input ready_in;
|
||||
input [IDW-1:0] coreid;
|
||||
|
||||
//core name for trace
|
||||
reg [31:0] ftrace;
|
||||
reg [255:0] tracefile;
|
||||
|
||||
//Dumps into
|
||||
initial
|
||||
begin
|
||||
//TODO: Figure out these delays
|
||||
#10
|
||||
//index should be core ID
|
||||
$sformat(tracefile,"%0s_%0h%s",NAME,coreid,".trace");
|
||||
ftrace = $fopen({tracefile}, "w");
|
||||
end
|
||||
|
||||
always @ (posedge clk or negedge nreset)
|
||||
if(nreset & dut_access & ready_in)
|
||||
begin
|
||||
$fwrite(ftrace, "%h_%h_%h_%h\n",dut_packet[PW-1:72],dut_packet[71:40],dut_packet[39:8],dut_packet[7:0]);
|
||||
//$display("%h_%h_%h_%h\n",dut_packet[PW-1:72],dut_packet[71:40],dut_packet[39:8],dut_packet[7:0]);
|
||||
end
|
||||
endmodule // dut_monitor
|
||||
|
||||
|
||||
|
||||
|
||||
@ -1,240 +0,0 @@
|
||||
|
||||
module ememory # (parameter AW = 32, // address width
|
||||
parameter PW = 104, // packet width
|
||||
parameter IDW = 12, // ID width
|
||||
parameter DEPTH = 65536, // memory depth
|
||||
parameter NAME = "emem", // instance name
|
||||
parameter WAIT = 0, // enable random wait
|
||||
parameter MON = 0 // enable monitor monitor
|
||||
)
|
||||
|
||||
(// clk,reset
|
||||
input clk,
|
||||
input nreset,
|
||||
input [IDW-1:0] coreid,
|
||||
// incoming read/write
|
||||
input access_in,
|
||||
input [PW-1:0] packet_in,
|
||||
output ready_out, //pushback
|
||||
// back to mesh (readback data)
|
||||
output reg access_out,
|
||||
output [PW-1:0] packet_out,
|
||||
input ready_in //pushback
|
||||
);
|
||||
|
||||
//derived parameters
|
||||
localparam DW = AW; //always the same
|
||||
parameter MAW = $clog2(DEPTH);
|
||||
|
||||
//###############
|
||||
//# LOCAL WIRES
|
||||
//##############
|
||||
|
||||
wire [MAW-1:0] addr;
|
||||
wire [63:0] din;
|
||||
wire [63:0] dout;
|
||||
wire en;
|
||||
wire mem_rd;
|
||||
reg [7:0] wen;
|
||||
reg write_out;
|
||||
reg [1:0] datamode_out;
|
||||
reg [4:0] ctrlmode_out;
|
||||
reg [AW-1:0] dstaddr_out;
|
||||
wire [AW-1:0] srcaddr_out;
|
||||
wire [AW-1:0] data_out;
|
||||
reg [2:0] align_addr;
|
||||
wire [DW-1:0] din_aligned;
|
||||
wire [63:0] dout_aligned;
|
||||
wire ready_random; //TODO: make random
|
||||
wire ready_all;
|
||||
/*AUTOWIRE*/
|
||||
// Beginning of automatic wires (for undeclared instantiated-module outputs)
|
||||
wire [4:0] ctrlmode_in; // From p2e of packet2emesh.v
|
||||
wire [AW-1:0] data_in; // From p2e of packet2emesh.v
|
||||
wire [1:0] datamode_in; // From p2e of packet2emesh.v
|
||||
wire [AW-1:0] dstaddr_in; // From p2e of packet2emesh.v
|
||||
wire [AW-1:0] srcaddr_in; // From p2e of packet2emesh.v
|
||||
wire write_in; // From p2e of packet2emesh.v
|
||||
// End of automatics
|
||||
|
||||
packet2emesh #(.AW(AW),
|
||||
.PW(PW))
|
||||
p2e (/*AUTOINST*/
|
||||
// Outputs
|
||||
.write_in (write_in),
|
||||
.datamode_in (datamode_in[1:0]),
|
||||
.ctrlmode_in (ctrlmode_in[4:0]),
|
||||
.dstaddr_in (dstaddr_in[AW-1:0]),
|
||||
.srcaddr_in (srcaddr_in[AW-1:0]),
|
||||
.data_in (data_in[AW-1:0]),
|
||||
// Inputs
|
||||
.packet_in (packet_in[PW-1:0]));
|
||||
|
||||
|
||||
//Access-in
|
||||
assign en = access_in & ready_all & ready_all;
|
||||
assign mem_rd = (access_in & ~write_in & ready_all);
|
||||
|
||||
|
||||
//Pushback Circuit (pass through problems?)
|
||||
assign ready_all = (ready_random | ready_in);
|
||||
assign readt_out = ready_all;// & access_in
|
||||
|
||||
//Address-in (shifted by three bits, 64 bit wide memory)
|
||||
assign addr[MAW-1:0] = dstaddr_in[MAW+2:3];
|
||||
|
||||
//Shift up
|
||||
assign din_aligned[DW-1:0] = (datamode_in[1:0]==2'b00) ? {(4){data_in[7:0]}} :
|
||||
(datamode_in[1:0]==2'b01) ? {(2){data_in[15:0]}} :
|
||||
data_in[31:0];
|
||||
|
||||
//Data-in (hardoded width)
|
||||
assign din[63:0] =(datamode_in[1:0]==2'b11) ? {srcaddr_in[31:0],din_aligned[31:0]}:
|
||||
{din_aligned[31:0],din_aligned[31:0]};
|
||||
//Write mask
|
||||
//TODO: make module
|
||||
always@*
|
||||
casez({write_in, datamode_in[1:0],dstaddr_in[2:0]})
|
||||
//Byte
|
||||
6'b100000 : wen[7:0] = 8'b00000001;
|
||||
6'b100001 : wen[7:0] = 8'b00000010;
|
||||
6'b100010 : wen[7:0] = 8'b00000100;
|
||||
6'b100011 : wen[7:0] = 8'b00001000;
|
||||
6'b100100 : wen[7:0] = 8'b00010000;
|
||||
6'b100101 : wen[7:0] = 8'b00100000;
|
||||
6'b100110 : wen[7:0] = 8'b01000000;
|
||||
6'b100111 : wen[7:0] = 8'b10000000;
|
||||
//Short
|
||||
6'b10100? : wen[7:0] = 8'b00000011;
|
||||
6'b10101? : wen[7:0] = 8'b00001100;
|
||||
6'b10110? : wen[7:0] = 8'b00110000;
|
||||
6'b10111? : wen[7:0] = 8'b11000000;
|
||||
//Word
|
||||
6'b1100?? : wen[7:0] = 8'b00001111;
|
||||
6'b1101?? : wen[7:0] = 8'b11110000;
|
||||
//Double
|
||||
6'b111??? : wen[7:0] = 8'b11111111;
|
||||
default : wen[7:0] = 8'b00000000;
|
||||
endcase // casez ({write, datamode_in[1:0],addr_in[2:0]})
|
||||
|
||||
//Single ported memory
|
||||
defparam mem.DW=64;
|
||||
defparam mem.DEPTH=DEPTH;
|
||||
oh_memory_sp mem(
|
||||
// Inputs
|
||||
.clk (clk),
|
||||
.en (en),
|
||||
.we (write_in),
|
||||
.wem ({
|
||||
{(8){wen[7]}},
|
||||
{(8){wen[6]}},
|
||||
{(8){wen[5]}},
|
||||
{(8){wen[4]}},
|
||||
{(8){wen[3]}},
|
||||
{(8){wen[2]}},
|
||||
{(8){wen[1]}},
|
||||
{(8){wen[0]}}
|
||||
}
|
||||
),
|
||||
.addr (addr[MAW-1:0]),
|
||||
.din (din[63:0]),
|
||||
.dout (dout[63:0]),
|
||||
.vdd (1'b1),
|
||||
.vddm (1'b1),
|
||||
.memrepair(8'b0),
|
||||
.memconfig(8'b0),
|
||||
.bist_en (1'b0),
|
||||
.bist_we (1'b0),
|
||||
.bist_wem (64'b0),
|
||||
.bist_addr({(MAW){1'b0}}),
|
||||
.bist_din (64'b0)
|
||||
);
|
||||
|
||||
//Outgoing transaction
|
||||
always @ (posedge clk or negedge nreset)
|
||||
if(!nreset)
|
||||
access_out <=1'b0;
|
||||
else
|
||||
begin
|
||||
access_out <= mem_rd;
|
||||
write_out <= 1'b1;
|
||||
align_addr[2:0] <= dstaddr_in[2:0];
|
||||
datamode_out[1:0] <= datamode_in[1:0];
|
||||
ctrlmode_out[4:0] <= ctrlmode_in[4:0];
|
||||
dstaddr_out[AW-1:0] <= srcaddr_in[AW-1:0];
|
||||
end
|
||||
|
||||
//Data alignment for readback
|
||||
emesh_rdalign emesh_rdalign (// Outputs
|
||||
.data_out (dout_aligned[63:0]),
|
||||
// Inputs
|
||||
.datamode (datamode_out[1:0]),
|
||||
.addr (align_addr[2:0]),
|
||||
.data_in (dout[63:0]));
|
||||
|
||||
assign srcaddr_out[AW-1:0] = (datamode_out[1:0]==2'b11) ? dout[63:32] : 32'b0;
|
||||
assign data_out[31:0] = dout_aligned[31:0];
|
||||
|
||||
//Concatenate
|
||||
emesh2packet #(.AW(AW),
|
||||
.PW(PW))
|
||||
e2p (
|
||||
/*AUTOINST*/
|
||||
// Outputs
|
||||
.packet_out (packet_out[PW-1:0]),
|
||||
// Inputs
|
||||
.write_out (write_out),
|
||||
.datamode_out (datamode_out[1:0]),
|
||||
.ctrlmode_out (ctrlmode_out[4:0]),
|
||||
.dstaddr_out (dstaddr_out[AW-1:0]),
|
||||
.data_out (data_out[AW-1:0]),
|
||||
.srcaddr_out (srcaddr_out[AW-1:0]));
|
||||
|
||||
|
||||
`ifdef TARGET_SIM
|
||||
generate
|
||||
if(MON)
|
||||
begin
|
||||
emesh_monitor #(.PW(PW),
|
||||
.INDEX(1),
|
||||
.NAME(NAME),
|
||||
.IDW(IDW)
|
||||
)
|
||||
emesh_monitor (.dut_access (access_in & write_in),
|
||||
.dut_packet (packet_in[PW-1:0]),
|
||||
.ready_in (ready_random),
|
||||
/*AUTOINST*/
|
||||
// Inputs
|
||||
.clk (clk),
|
||||
.nreset (nreset),
|
||||
.coreid (coreid[IDW-1:0]));
|
||||
end // if (MON)
|
||||
endgenerate
|
||||
`endif
|
||||
|
||||
//Random wait generator //TODO: make this a module
|
||||
generate
|
||||
if(WAIT)
|
||||
begin
|
||||
reg [8:0] ready_counter;
|
||||
always @ (posedge clk or negedge nreset)
|
||||
if(!nreset)
|
||||
ready_counter[8:0] <= 'b0;
|
||||
else
|
||||
ready_counter[8:0] <= ready_counter+1'b1;
|
||||
assign ready_random = (|ready_counter[5:0]);//(|ready_counter[3:0]);//1'b0;
|
||||
end
|
||||
else
|
||||
begin
|
||||
assign ready_random = 1'b0;
|
||||
end // else: !if(WAIT)
|
||||
endgenerate
|
||||
|
||||
|
||||
endmodule // emesh_memory
|
||||
// Local Variables:
|
||||
// verilog-library-directories:("." "../dv" )
|
||||
// End:
|
||||
|
||||
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user