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Updating interface description
This commit is contained in:
Andreas Olofsson
parent
f908acc259
commit
617e5f76de
@ -48,7 +48,6 @@ elink
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| |----etx_mmu (advanced dstaddr mapping)
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| |----etx_cfgif (configuration interface)
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| |----etx_cfg (basic rx config registers)
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| |----etx_dma (DMA master)
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| |----etx_arbiter (sends rx transaction to WR/RD/RR fifo)
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|----etx_fifo
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|----txwr_fifo (write fifo)
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@ -125,27 +124,30 @@ The elink has the following clock domains:
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*txo_lclk90: The txo_lclk phase shifted by 90 degrees. Used by RX to sample the dual data rate data.
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###INTERFACE SIGNALS
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###INTERFACE SIGNALS
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SIGNAL |DIR| DESCRIPTION
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------------------|---|--------------
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txo_frame_{p/n} | O | TX packet framing signal
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txo_lclk{p/n} | O | TX clock aligned in the center of the data eye
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txo_data{p/n}[7:0]| O | TX dual data rate (DDR) that transmits packet
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txi_rd_wait{p/n} | I | TX push back (input) for read transactions
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txi_wd_wait{p/n} | I | TX push back (input) for write transactions
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rxi_frame{p/n} | I | RX packet framing signal.
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rxi_lclk{p/n} | I | RX clock aligned in the center of the data eye
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rxi_data{p/n}[7:0]| I | RX dual data rate (DDR) that transmits packet
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rxo_rd_wait{p/n} | O | RX push back (output) for read transactions
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rxo_wr_wait{p/n} | O | RX push back (output) for write transactions
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reset | I | Reset input
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pll_clk | I | Clock input for CCLK/LCLK PLL
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sys_clk | I | System clock for FIFOs
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embox_not_empty | O | Mailbox not empty (connect to interrupt line)
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embox_full | O | Mailbox is full indicator
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m_* |IO | AXI master interface
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s_* |IO | AXI slave interface
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SIGNAL | DIR| DESCRIPTION
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-------------------|----|--------------
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m_* | IO | AXI master interface
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s_* | IO | AXI slave interface
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txo_frame_{p/n} | O | TX packet framing signal
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txo_lclk_{p/n} | O | TX clock aligned in the center of the data eye
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txo_data_{p/n}[7:0]| O | TX dual data rate (DDR) that transmits packet
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txi_rd_wait_{p/n} | I | TX push back (input) for read transactions
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txi_wd_wait{p/n} | I | TX push back (input) for write transactions
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rxi_frame_{p/n} | I | RX packet framing signal.
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rxi_lclk_{p/n} | I | RX clock aligned in the center of the data eye
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rxi_data_{p/n}[7:0]| I | RX dual data rate (DDR) that transmits packet
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rxo_rd_wait_{p/n} | O | RX push back (output) for read transactions
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rxo_wr_wait_{p/n} | O | RX push back (output) for write transactions
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reset | I | Reset input
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pll_clk | I | Clock input for CCLK/LCLK PLL
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sys_clk | I | System clock for FIFOs
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embox_not_empty | O | Mailbox not empty (connect to interrupt line)
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embox_full | O | Mailbox is full indicator
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e_chipid[11:0] | O | ID for Epiphany chip (optional)
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e_resetb | O | Active low reset for Epiphany chip (optional)
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e_cclk_{p/n} | O | High speed clock for Epiphany chip (optional)
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###FPGA RESOURCE USAGE
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The following table shows the rough resource usage of the elink synthesized with the xc7z010clg400-1 as a target.
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@ -192,37 +194,29 @@ REGISTER | AC | ADDRESS | DESCRIPTION
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---------------|----|---------|------------------
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E_RESET | -W | 0xF0200 | Soft reset
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E_CLK | -W | 0xF0204 | Clock configuration
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E_CHIPID | RW | 0xF0208 | Chip ID for Epiphany pins
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E_CHIPID | RW | 0xF0208 | Chip ID for Epiphany pins
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E_VERSION | RW | 0xF020C | Version number (static)
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E_MAILBOXLO | RW | 0xF0310 | RX mailbox (lower 32 bit)
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E_MAILBOXHI | RW | 0xF0314 | RX mailbox (upper 32 bits)
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***************|****|*********|**************************
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E_VERSION | RW | 0xF020C | Version number (static)
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ETX_CFG | RW | 0xF0210 | TX configuration
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ETX_STATUS | R- | 0xF0214 | TX status
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ETX_GPIO | RW | 0xF0218 | TX data in GPIO mode
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ETX_DMACFG | RW | 0xF0500 | RX DMA configuration
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ETX_DMACOUNT | RW | 0xF0504 | RX DMA count
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ETX_DMASTRIDE | RW | 0xF0508 | RX DMA stride
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ETX_DMASRCADDR | RW | 0xF050c | RX DMA source addres
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ETX_DMADSTADDR | RW | 0xF0510 | RX DMA slave buffer (lo)
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ETX_DMAAUTO0 | RW | 0xF0514 | RX DMA slave buffer (hi)
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ETX_DMAAUTO1 | RW | 0xF0518 | RX DMA slave buffer (hi)
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ETX_DMASTATUS | RW | 0xF051c | RX DMA status
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***************|****|*********|********************
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ETX_MMU | -W | 0xE0000 | TX MMU table
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***************|****|*********|********************
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ERX_CFG | RW | 0xF0300 | RX configuration
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ERX_STATUS | R- | 0xF0304 | RX status register
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ERX_GPIO | R | 0xF0308 | RX data in GPIO mode
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ERX_OFFSET | RW | 0xF030C | RX memory offset in remap mode
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E_MAILBOXLO | RW | 0xF0310 | RX mailbox (lower 32 bit)
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E_MAILBOXHI | RW | 0xF0314 | RX mailbox (upper 32 bits)
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ERX_DMACFG | RW | 0xF0520 | TX DMA configuration
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ERX_DMACOUNT | RW | 0xF0524 | TX DMA count
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ERX_DMASTRIDE | RW | 0xF0528 | TX DMA stride
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ETX_DMASRCADDR | RW | 0xF052c | TX DMA source addres
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ERX_DMADSTADDR | RW | 0xF0530 | TX DMA destination address
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ERX_DMAAUTO0 | RW | 0xF0534 | TX DMA slave buffer (lo)
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ERX_DMAAUTO1 | RW | 0xF0538 | TX DMA slERXave buffer (hi)
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ERX_DMASTATUS | RW | 0xF053c | TX DMA status
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ERX_OFFSET | RW | 0xF030C | RX mem offset in remap mode
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ERX_DMACFG | RW | 0xF0520 | RX DMA configuration
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ERX_DMACOUNT | RW | 0xF0524 | RX DMA count
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ERX_DMASTRIDE | RW | 0xF0528 | RX DMA stride
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ERX_DMASRCADDR | RW | 0xF052c | RX DMA source addres
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ERX_DMADSTADDR | RW | 0xF0530 | RX DMA destination address
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ERX_DMAAUTO0 | RW | 0xF0534 | RX DMA slave buffer (lo)
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ERX_DMAAUTO1 | RW | 0xF0538 | RX DMA slERXave buffer (hi)
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ERX_DMASTATUS | RW | 0xF053c | RX DMA status
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***************|****|*********|********************
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ERX_MMU | -W | 0xE8000 | RX MMU table
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@ -391,7 +385,7 @@ FIELD | DESCRIPTION
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-------- |---------------------------------------------------
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[31:0] | Upper data of RX FIFO
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###DMACFG (0xF0500/0xF0520)
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###EXR_DMACFG (0xF0500)
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Configuration register for DMA.
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FIELD | DESCRIPTION
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@ -411,14 +405,14 @@ FIELD | DESCRIPTION
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[12] | 0: Destination address shift disabled
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| 1: Left shifts stride by 16 bits
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###DMACOUNT (0xF0504/0xF0524)
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###ERX_DMACOUNT (0xF0504)
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The number of DMA left to complete The DMA transfer is complete when the DMACOUNT register reaches zero.
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FIELD | DESCRIPTION
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-------- |---------------------------------------------------
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[31:0] | The number of transfers remaining
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###DMASTRIDE (0xF0508/0xF0528)
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###ERX_DMASTRIDE (0xF0508)
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Two signed 16-bit values specifying the stride, in bytes, used to update the DMASRCADDR and DMADSTADDR after each completed transfer.
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FIELD | DESCRIPTION
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@ -426,14 +420,14 @@ FIELD | DESCRIPTION
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[15:0] | Value to add to DMASRCADDR after each transaction
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[31:16] | Value to add to DMADSTADDR after each transaction
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###DMASRCADDR (0xF050C/0xF052C)
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###ERX_DMASRCADDR (0xF050C)
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The current 32-bit address being read from in master mode.
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FIELD | DESCRIPTION
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-------- |---------------------------------------------------
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[31:0] | Current transaction destination address to write to
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###DMADSTADDR (0xF0510/0xF0530)
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###ERX_DMADSTADDR (0xF0510)
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The current 32-bit address being transferred.
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FIELD | DESCRIPTION
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@ -441,7 +435,7 @@ FIELD | DESCRIPTION
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[31:0] | Current transaction destination address to write to
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###DMAAUTO0 (0xF0514/0xF0534)
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###ERX_DMAAUTO0 (0xF0514)
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Auto DMA register
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FIELD | DESCRIPTION
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@ -449,7 +443,7 @@ FIELD | DESCRIPTION
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[31:0] | TBD
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###DMAAUTO1 (0xF0518/0xF0538)
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###ERX_DMAAUTO1 (0xF0518)
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Auto DMA register
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FIELD | DESCRIPTION
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