Adding comments

xilibs/hdl/BUFIO.v

@@ -1,3 +1,22 @@
+/*###########################################################################
+ *#An I/O clock buffer
+ *########################################################################### 
+ * 
+ * BUIOs can drive:
+ * -a single I/O clock network in the same region/bank
+ * 
+ * BUIOs can be driven by:
+ * -SRCCs and MRCCs in the same clock region
+ * -MRCCs in an adjacent clock region using BUFMRs
+ * -MMCMs clock outputs 0-3 driving the HPC in the same clock region
+ *
+ * 
+ * Input to Output Delay (Zynq7010/7020): 1.61/1.32/1.16 (-1/-2/-3 grade) 
+ * 
+ * 
+ */ 
+
+
 module BUFIO (/*AUTOARG*/
    // Outputs
    O,

xilibs/hdl/BUFR.v

@@ -1,3 +1,24 @@
+/*###########################################################################
+ *#Clock buffer with built in divider
+ *########################################################################### 
+ *
+ * Division ratios: 1,2,3,4,5,6,7,8, and bypass division ratings
+ * 
+ * BUFRs can drive:
+ * -I/O logic
+ * -logic resources
+ * 
+ * BUFRs can be driven by:
+ * -SRCCs and MRCCs in the same clock region
+ * -MRCCs in an adjacent clock region using BUFMRs
+ * -MMCMs clock outputs 0-3 driving the HPC in the same clock region
+ * -MMCMs clock outputs 0-3
+ * -General interconnect 
+ * 
+ * Input to Output Delay (Zynq7010/7020): 1.04/0.80/0.64 (-1/-2/-3 grade) 
+ * 
+ */ 
+
 module BUFR (/*AUTOARG*/
    // Outputs
    O,
@@ -8,10 +29,10 @@ module BUFR (/*AUTOARG*/
    parameter BUFR_DIVIDE=4;
    parameter SIM_DEVICE=0;
 
-   input I;
-   input CE;
-   input CLR;
-   output O;
+   input I;   //clock input
+   input CE;  //async output clock enable
+   input CLR; //async clear for divider logic
+   output O;  //clock output
 
   
    //assign O=I & CE & ~CLR;

xilibs/hdl/IBUFDS.v

@@ -1,3 +1,4 @@
+
 module IBUFDS (/*AUTOARG*/
    // Outputs
    O,

xilibs/hdl/IBUFGDS.v

@@ -1,3 +1,4 @@
+
 module IBUFGDS (/*AUTOARG*/
    // Outputs
    O,