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Directory strcuture change
-hdl-->rtl (more common...)
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@ -31,14 +31,13 @@ module oh_padring
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parameter WE_VDD = 8,
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parameter WE_VSS = 8,
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parameter ENABLE_CUT = 1,
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parameter ENABLE_POC = 1,
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parameter TECH_CFG_WIDTH = 16,
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parameter ENABLE_POC = 1,
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parameter TECH_CFG_WIDTH = 16,
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parameter TECH_RING_WIDTH = 8
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)
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(
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//CONTINUOUS GROUND
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inout vss,
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inout vdd,
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//NORTH
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inout [NO_DOMAINS-1:0] no_vddio,
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@ -82,7 +81,6 @@ module oh_padring
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inout [WE_GPIO*TECH_CFG_WIDTH-1:0] we_tech_cfg
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);
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//Local wires
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wire [NO_DOMAINS-1:0] no_poc;
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wire [SO_DOMAINS-1:0] so_poc;
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@ -19,22 +19,21 @@ module oh_pads_domain
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parameter TECH_RING_WIDTH = 8
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)
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(//pad
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inout [NGPIO-1:0] pad, // pad
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inout [NGPIO-1:0] pad, // pad
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//feed through signals
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inout vddio, // io supply
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inout vssio, // io ground
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inout vdd, // core supply
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inout vss, // common ground
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inout poc, // power-on-ctrl
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inout [TECH_RING_WIDTH-1:0] ring,
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inout vddio, // io supply
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inout vssio, // io ground
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inout vdd, // core supply
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inout vss, // common ground
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inout poc, // power-on-ctrl
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inout [TECH_RING_WIDTH-1:0] ring,
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//core facing signals
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input [NGPIO-1:0] dout, // data to drive to pad
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output [NGPIO-1:0] din, // data from pad
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input [NGPIO-1:0] oen, // output enable (bar)
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input [NGPIO-1:0] ie, // input enable
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input [NGPIO*8-1:0] cfg, // io config
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input [NGPIO-1:0] dout, // data to drive to pad
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output [NGPIO-1:0] din, // data from pad
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input [NGPIO-1:0] oen, // output enable (bar)
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input [NGPIO-1:0] ie, // input enable
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input [NGPIO*8-1:0] cfg, // io config
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inout [NGPIO*TECH_CFG_WIDTH-1:0] tech_cfg // technology-specific config
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);
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@ -179,6 +178,3 @@ endmodule
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// Local Variables:
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// verilog-library-directories:("." )
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// End:
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