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Making reset async

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This commit is contained in:
Andreas Olofsson 2015-10-07 12:06:30 -04:00
parent a39966d9f1
commit 634b1f81f0
1 changed files with 1 additions and 1 deletions
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emmu/hdl/emmu.v
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@ -125,7 +125,7 @@ module emmu (/*AUTOARG*/
//assumes one cycle memory access! //assumes one cycle memory access!
always @ (posedge rd_clk) always @ (posedge rd_clk or posedge reset)
if (reset) if (reset)
begin begin
emesh_access_out <= 1'b0; emesh_access_out <= 1'b0;