FPGA/oh
1
0
Fork 0
mirror of https://github.com/aolofsson/oh.git synced 2025-01-17 20:02:53 +08:00
Code Issues Projects Releases Wiki Activity

Bug fixes

Browse Source
This commit is contained in:
Patrik Lindström 2015-06-30 13:32:05 +02:00
parent 48fdf2d782
commit 634ff371ac
17 changed files with 69 additions and 27 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
elink/hdl/ecfg_elink.v
View File

@ -4,6 +4,8 @@
########################################################################
*/
`include "elink_regmap.v"
module ecfg_elink (/*AUTOARG*/
// Outputs
txwr_gated_access, elink_en, clk_config, e_chipid,

3
elink/hdl/eclocks.v
View File

@ -13,6 +13,9 @@
############################################################################
*/
//`define TARGET_XILINX //TODO this need to be global
`include elink_constants.v
module eclocks (/*AUTOARG*/
// Outputs
tx_lclk, tx_lclk90, tx_lclk_div4, rx_lclk, rx_lclk_div4,

3
elink/hdl/elink.v
View File

@ -19,6 +19,7 @@ module elink(/*AUTOARG*/
parameter DW = 32;
parameter PW = 104; //packet width
parameter ID = 12'h810;
parameter IOSTD_ELINK = "LVDS_25";
/****************************/
/*CLK AND RESET */
@ -172,6 +173,7 @@ module elink(/*AUTOARG*/
*/
defparam erx.ID=ID;
defparam erx.IOSTD_ELINK=IOSTD_ELINK;
erx erx(
/*AUTOINST*/
// Outputs
@ -222,6 +224,7 @@ module elink(/*AUTOARG*/
*/
defparam etx.ID=ID;
defparam etx.IOSTD_ELINK=IOSTD_ELINK;
etx etx(.txwr_access (txwr_gated_access),
/*AUTOINST*/
// Outputs

5
elink/hdl/elink_constants.v
View File

@ -1,6 +1,11 @@
`ifndef ELINK_CONSTANTS_V_
`define ELINK_CONSTANTS_V_
//These constants are mutually exclusive
`define TARGET_XILINX
`define CFG_AW 32
`define CFG_DW 32
`define CFG_LW 8
`define CFG_NW 13 /*Number of bytes in the transmission*/
`endif

5
elink/hdl/elink_regmap.v
View File

@ -1,3 +1,6 @@
`ifndef ELINK_REGMAP_V_
`define ELINK_REGMAP_V_
//MEMORY MAP
//[31:20] = LINKID
@ -39,3 +42,5 @@
`define DMAAUTO0 5'd5 //F0514/F0534
`define DMAAUTO1 5'd6 //F0518/F0538
`define DMASTATUS 5'd7 //F051C/F053c
`endif

40
elink/hdl/emaxi.v
View File

@ -138,6 +138,7 @@ module emaxi(/*autoarg*/
reg [2:0] m_axi_awsize;
reg m_axi_awvalid;
reg [63 : 0] m_axi_wdata;
reg [63 : 0] m_axi_rdata_reg;
reg [7 : 0] m_axi_wstrb;
reg m_axi_wlast;
reg m_axi_wvalid;
@ -441,6 +442,13 @@ module emaxi(/*autoarg*/
assign m_axi_rready = ~txrr_wait; //pass through
always @( posedge m_axi_aclk )
if ( ~m_axi_aresetn )
m_axi_rdata_reg <= 'b0;
else
m_axi_rdata_reg <= m_axi_rdata;
always @( posedge m_axi_aclk )
if( ~m_axi_aresetn )
begin
@ -459,32 +467,32 @@ module emaxi(/*autoarg*/
case(readinfo_out[1:0])//datamode
2'd0: // byte read
case(readinfo_out[8:6])
3'd0: txrr_data[7:0] <= m_axi_rdata[7:0];
3'd1: txrr_data[7:0] <= m_axi_rdata[15:8];
3'd2: txrr_data[7:0] <= m_axi_rdata[23:16];
3'd3: txrr_data[7:0] <= m_axi_rdata[31:24];
3'd4: txrr_data[7:0] <= m_axi_rdata[39:32];
3'd5: txrr_data[7:0] <= m_axi_rdata[47:40];
3'd6: txrr_data[7:0] <= m_axi_rdata[55:48];
default: txrr_data[7:0] <= m_axi_rdata[63:56];
3'd0: txrr_data[7:0] <= m_axi_rdata_reg[7:0];
3'd1: txrr_data[7:0] <= m_axi_rdata_reg[15:8];
3'd2: txrr_data[7:0] <= m_axi_rdata_reg[23:16];
3'd3: txrr_data[7:0] <= m_axi_rdata_reg[31:24];
3'd4: txrr_data[7:0] <= m_axi_rdata_reg[39:32];
3'd5: txrr_data[7:0] <= m_axi_rdata_reg[47:40];
3'd6: txrr_data[7:0] <= m_axi_rdata_reg[55:48];
default: txrr_data[7:0] <= m_axi_rdata_reg[63:56];
endcase
2'd1: // 16b hword
case( readinfo_out[8:7] )
2'd0: txrr_data[15:0] <= m_axi_rdata[15:0];
2'd1: txrr_data[15:0] <= m_axi_rdata[31:16];
2'd2: txrr_data[15:0] <= m_axi_rdata[47:32];
default: txrr_data[15:0] <= m_axi_rdata[63:48];
2'd0: txrr_data[15:0] <= m_axi_rdata_reg[15:0];
2'd1: txrr_data[15:0] <= m_axi_rdata_reg[31:16];
2'd2: txrr_data[15:0] <= m_axi_rdata_reg[47:32];
default: txrr_data[15:0] <= m_axi_rdata_reg[63:48];
endcase
2'd2: // 32b word
if( readinfo_out[8] )
txrr_data[31:0] <= m_axi_rdata[63:32];
txrr_data[31:0] <= m_axi_rdata_reg[63:32];
else
txrr_data[31:0] <= m_axi_rdata[31:0];
txrr_data[31:0] <= m_axi_rdata_reg[31:0];
// 64b word already defined by defaults above
2'd3:
begin // 64b dword
txrr_data[31:0] <= m_axi_rdata[31:0];
txrr_srcaddr[31:0] <= m_axi_rdata[63:32];
txrr_data[31:0] <= m_axi_rdata_reg[31:0];
txrr_srcaddr[31:0] <= m_axi_rdata_reg[63:32];
end
endcase
end // else: !if( ~m_axi_aresetn )

2
elink/hdl/erx.v
View File

@ -16,6 +16,7 @@ module erx (/*AUTOARG*/
parameter PW = 104;
parameter RFAW = 6;
parameter ID = 12'h800;
parameter IOSTD_ELINK="LVDS_25";
//Synched resets
input erx_reset; // reset for core logic
@ -84,6 +85,7 @@ module erx (/*AUTOARG*/
/***********************************************************/
/*RECEIVER I/O LOGIC */
/***********************************************************/
defparam erx_io.IOSTD_ELINK=IOSTD_ELINK;
erx_io erx_io (.reset (erx_reset),
/*AUTOINST*/
// Outputs

3
elink/hdl/erx_arbiter.v
View File

@ -1,3 +1,4 @@
`include "elink_regmap.v"
module erx_arbiter (/*AUTOARG*/
// Outputs
rx_rd_wait, rx_wr_wait, edma_wait, ecfg_wait, rxwr_access,
@ -108,7 +109,7 @@ module erx_arbiter (/*AUTOARG*/
assign erx_rr_access = (erx_access &
erx_write &
(erx_dstaddr[31:20] == myid[11:0]) &
(erx_dstaddr[19:16] == 4'hD)
(erx_dstaddr[19:16] == `EGROUP_RR) // Not sure about this...
);
assign rxrr_access = erx_rr_access |

1
elink/hdl/erx_cfg.v
View File

@ -4,6 +4,7 @@
########################################################################
*/
`include "elink_regmap.v"
module erx_cfg (/*AUTOARG*/
// Outputs

17
elink/hdl/erx_io.v
View File

@ -8,7 +8,7 @@ module erx_io (/*AUTOARG*/
rx_rd_wait
);
parameter IOSTANDARD = "LVDS_25";
parameter IOSTD_ELINK = "LVDS_25";
parameter PW = 104;
//#########################
@ -47,6 +47,7 @@ module erx_io (/*AUTOARG*/
wire access_wide;
reg valid_packet;
wire [15:0] rx_word;
wire rx_ref_clk_idlyctrl;
//############
//# REGS
@ -179,32 +180,32 @@ module erx_io (/*AUTOARG*/
//# I/O Buffers Instantiation
//################################
IBUFDS #(.DIFF_TERM ("TRUE"),.IOSTANDARD (IOSTANDARD))
IBUFDS #(.DIFF_TERM ("TRUE"),.IOSTANDARD (IOSTD_ELINK))
ibuf_data[7:0]
(.I (rxi_data_p[7:0]),
.IB (rxi_data_n[7:0]),
.O (rxi_data[7:0]));
IBUFDS #(.DIFF_TERM ("TRUE"), .IOSTANDARD (IOSTANDARD))
IBUFDS #(.DIFF_TERM ("TRUE"), .IOSTANDARD (IOSTD_ELINK))
ibuf_frame
(.I (rxi_frame_p),
.IB (rxi_frame_n),
.O (rxi_frame));
IBUFDS #(.DIFF_TERM ("TRUE"),.IOSTANDARD (IOSTANDARD))
IBUFDS #(.DIFF_TERM ("TRUE"),.IOSTANDARD (IOSTD_ELINK))
ibuf_lclk (.I (rxi_lclk_p),
.IB (rxi_lclk_n),
.O (rxi_lclk)
);
OBUFDS #(.IOSTANDARD(IOSTANDARD),.SLEW("SLOW"))
OBUFDS #(.IOSTANDARD(IOSTD_ELINK),.SLEW("SLOW"))
obufds_wrwait (
.O(rxo_wr_wait_p),
.OB(rxo_wr_wait_n),
.I(rx_wr_wait)
);
OBUFDS #(.IOSTANDARD(IOSTANDARD),.SLEW("SLOW"))
OBUFDS #(.IOSTANDARD(IOSTD_ELINK),.SLEW("SLOW"))
obufds_rdwait (.O(rxo_rd_wait_p),
.OB(rxo_rd_wait_n),
.I(rx_rd_wait)
@ -222,9 +223,11 @@ module erx_io (/*AUTOARG*/
assign rxi_delay_in[8:0] ={rxi_frame,rxi_data[7:0]};
BUFG bufg_rx_ref_clk( .I(rx_ref_clk), .O(rx_ref_clk_idlyctrl));
//Do these need parameters?
IDELAYCTRL idelayctrl_inst (.RDY(),
.REFCLK(rx_ref_clk),//200MHz clk (78ps tap delay)
.REFCLK(rx_ref_clk_idlyctrl),//200MHz clk (78ps tap delay)
.RST(1'b0)
);

3
elink/hdl/esaxi.v
View File

@ -1,3 +1,4 @@
`include "elink_regmap.v"
module esaxi (/*autoarg*/
// Outputs
txwr_access, txwr_packet, txrd_access, txrd_packet, rxrr_wait,
@ -266,6 +267,8 @@ module esaxi (/*autoarg*/
//###################################################
//#WRITE RESPONSE CHANNEL
//###################################################
assign s_axi_bid = axi_bid;
always @ (posedge s_axi_aclk)
if(~s_axi_aresetn)
s_axi_wready <= 1'b0;

2
elink/hdl/etx.v
View File

@ -14,6 +14,7 @@ module etx(/*AUTOARG*/
parameter PW = 104;
parameter RFAW = 6;
parameter ID = 12'h000;
parameter IOSTD_ELINK="LVDS_25";
//Synched resets
input etx_reset; // reset for core logic
@ -155,6 +156,7 @@ module etx(/*AUTOARG*/
/*TRANSMIT I/O LOGIC */
/***********************************************************/
defparam etx_io.IOSTD_ELINK=IOSTD_ELINK;
etx_io etx_io (.reset (etx_reset),
/*AUTOINST*/
// Outputs

1
elink/hdl/etx_cfg.v
View File

@ -3,6 +3,7 @@
ELINK TX CONFIGURATION REGISTER FILE
########################################################################
*/
`include "elink_regmap.v"
module etx_cfg (/*AUTOARG*/
// Outputs
mi_dout, tx_enable, mmu_enable, gpio_enable, remap_enable,

2
elink/hdl/etx_io.v
View File

@ -134,7 +134,7 @@ always @ (posedge tx_lclk)
always @ (posedge tx_lclk)
if (tx_new_frame)
tx_double[63:0] <= {16'b0,//16
write,7'b0,ctrlmode[3:0],//12
~write,7'b0,ctrlmode[3:0],//12
dstaddr[31:0],datamode[1:0],write,access};//36
else if(tx_state[2:0]==`CYCLE4)
tx_double[63:0] <= {data[31:0],srcaddr[31:0]};

2
elink/hdl/etx_protocol.v
View File

@ -1,3 +1,5 @@
`include "elink_regmap.v"
module etx_protocol (/*AUTOARG*/
// Outputs
etx_rd_wait, etx_wr_wait, tx_packet, tx_access, tx_burst,

1
emailbox/hdl/emailbox.v
View File

@ -18,6 +18,7 @@
#
###########################################################################
*/
`include "../../elink/hdl/elink_regmap.v" // is there a better way?
module emailbox (/*AUTOARG*/
// Outputs

2
memory/hdl/fifo_async.v
View File

@ -1,4 +1,4 @@
`include "../../elink/elink_constants.v"
module fifo_async
(/*AUTOARG*/
// Outputs