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Adding manual test feature to testbench
-This is as far as I go with fufu testing (random next) -Add basic test for cleaning up reads/writes -104 bit packet format for driving transactions, very useful
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Andreas Olofsson
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8adc060bc8
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643ceed432
@ -175,8 +175,8 @@ module dv_elink(/*AUTOARG*/
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//Clocks
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wire clkin = clk[0];
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wire m_axi_aclk = clk[1];
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wire clkin = clk[0]; //for pll-->cclk, rxclk, txclk
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wire m_axi_aclk = clk[1];
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wire s_axi_aclk = clk[1];
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//Splitting transaction into read/write path
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@ -366,7 +366,7 @@ module dv_elink(/*AUTOARG*/
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.s_axi_rvalid (elink_axi_rvalid), // Templated
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.s_axi_wready (elink_axi_wready), // Templated
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// Inputs
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.s_axi_araddr (elink_axi_araddr[29:0]), // Templated
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.s_axi_araddr (elink_axi_araddr[31:0]), // Templated
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.s_axi_arburst (elink_axi_arburst[1:0]), // Templated
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.s_axi_arcache (elink_axi_arcache[3:0]), // Templated
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.s_axi_arlen (elink_axi_arlen[7:0]), // Templated
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@ -374,7 +374,7 @@ module dv_elink(/*AUTOARG*/
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.s_axi_arqos (elink_axi_arqos[3:0]), // Templated
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.s_axi_arsize (elink_axi_arsize[2:0]), // Templated
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.s_axi_arvalid (elink_axi_arvalid), // Templated
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.s_axi_awaddr (elink_axi_awaddr[29:0]), // Templated
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.s_axi_awaddr (elink_axi_awaddr[31:0]), // Templated
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.s_axi_awburst (elink_axi_awburst[1:0]), // Templated
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.s_axi_awcache (elink_axi_awcache[3:0]), // Templated
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.s_axi_awlen (elink_axi_awlen[7:0]), // Templated
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@ -402,6 +402,8 @@ module dv_elink(/*AUTOARG*/
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);
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*/
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defparam elink.ELINKID = 12'h800;
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elink elink (.hard_reset (reset),
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.embox_not_empty (embox_full),
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.embox_full (embox_not_empty),
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@ -415,7 +417,7 @@ module dv_elink(/*AUTOARG*/
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.cclk_p (cclk_p),
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.cclk_n (cclk_n),
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.clkin (clkin),
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.bypass_clocks ({clkin,clkin,clkin}),
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.clkbypass ({clkin,clkin,clkin}),
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/*AUTOINST*/
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// Outputs
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.rxo_wr_wait_p (wr_wait_p), // Templated
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@ -479,7 +481,7 @@ module dv_elink(/*AUTOARG*/
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.m_axi_rresp (elink_axi_rresp[1:0]), // Templated
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.m_axi_rvalid (elink_axi_rvalid), // Templated
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.m_axi_wready (elink_axi_wready), // Templated
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.s_axi_araddr (dv_axi_araddr[29:0]), // Templated
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.s_axi_araddr (dv_axi_araddr[31:0]), // Templated
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.s_axi_arburst (dv_axi_arburst[1:0]), // Templated
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.s_axi_arcache (dv_axi_arcache[3:0]), // Templated
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.s_axi_arlen (dv_axi_arlen[7:0]), // Templated
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@ -487,7 +489,7 @@ module dv_elink(/*AUTOARG*/
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.s_axi_arqos (dv_axi_arqos[3:0]), // Templated
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.s_axi_arsize (dv_axi_arsize[2:0]), // Templated
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.s_axi_arvalid (dv_axi_arvalid), // Templated
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.s_axi_awaddr (dv_axi_awaddr[29:0]), // Templated
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.s_axi_awaddr (dv_axi_awaddr[31:0]), // Templated
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.s_axi_awburst (dv_axi_awburst[1:0]), // Templated
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.s_axi_awcache (dv_axi_awcache[3:0]), // Templated
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.s_axi_awlen (dv_axi_awlen[7:0]), // Templated
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@ -527,9 +529,9 @@ module dv_elink(/*AUTOARG*/
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emesh_monitor #(.NAME("stimulus")) ext_monitor (.emesh_wait ((dut_rd_wait | dut_wr_wait)),//TODO:fix collisions
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.clk (m_axi_aclk),
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/*AUTOINST*/
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// Inputs
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.clk (m_axi_aclk),
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.reset (reset),
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.itrace (itrace),
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.etime (etime[31:0]),
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@ -542,9 +544,9 @@ module dv_elink(/*AUTOARG*/
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.emesh_srcaddr (ext_srcaddr[AW-1:0])); // Templated
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emesh_monitor #(.NAME("dut")) dut_monitor (.emesh_wait (1'b0),
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.clk (s_axi_aclk),
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/*AUTOINST*/
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// Inputs
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.clk (s_axi_aclk),
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.reset (reset),
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.itrace (itrace),
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.etime (etime[31:0]),
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@ -1,7 +1,13 @@
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module dv_elink_tb();
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parameter AW=32;
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parameter DW=32;
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parameter CW=2; //number of clocks to send int
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parameter CW=2; //number of clocks to send int
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parameter MW=104;
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parameter MAW=10;
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parameter MD=1<<MAW;//limit test to 1K transactions
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//TODO:generealize
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/* verilator lint_off STMTDLY */
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/* verilator lint_off UNOPTFLAT */
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//REGS
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@ -19,18 +25,32 @@ module dv_elink_tb();
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reg ext_wr_wait;
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reg ext_rd_wait;
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reg init;
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reg [MW-1:0] stimarray[MD-1:0];
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reg [MW-1:0] transaction;
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reg [MAW-1:0] stim_addr;
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integer i;
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`ifdef MANUAL
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//TODO: make test name a parameter, fancify,...
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initial
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begin
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for(i=0;i<MD;i++)
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stimarray[i]='d0;
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//$readmemh(`TESTNAME,stimarray,0,`TRANS-1);//How to?
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$readmemh("test.memh",stimarray,0,`TRANS-1);
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end
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`endif
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//Forever clock
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always
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#10 clk[0] = ~clk[0];//clock for elink
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#1 clk[0] = ~clk[0];//clock for elink
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always
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#100 clk[1] = ~clk[1];//clock for axi interface
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#10 clk[1] = ~clk[1];//clock for axi interface
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//should make variable to really test all fifos
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wire clkstim = clk[1];
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//Reset
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initial
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begin
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@ -40,22 +60,22 @@ module dv_elink_tb();
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clk[1:0] = 2'b0;
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datamode = 2'b10;
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#400
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`ifdef AUTO
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//clock config (fast /2)
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dv_elink.elink.ecfg.ecfg_clk_reg[15:0] = 16'h0113;
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//tx config (enable)
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dv_elink.elink.ecfg.ecfg_tx_reg[8:0] = 9'h001;
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//rx config (enable)
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dv_elink.elink.ecfg.ecfg_rx_reg[4:0] = 5'h01;
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`endif
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reset = 1'b0; // at time 100 release reset
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#1000
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go = 1'b1;
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#2000
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datamode = 2'b01;
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#3000
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datamode = 2'b00;
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#4000
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`ifdef AUTO
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go = 1'b0;
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`endif
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#10000
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$finish;
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end
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@ -67,24 +87,38 @@ module dv_elink_tb();
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always @ (posedge clkstim)
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if(reset | ~go)
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begin
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ext_access <= 1'b0; //empty
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ext_write <= 1'b1;
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ext_datamode[1:0] <= 2'b0;
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ext_ctrlmode[3:0] <= 4'b0;
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ext_data[31:0] <= 32'b0;
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ext_dstaddr[31:0] <= 32'b0;
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ext_srcaddr[31:0] <= 32'b0;
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ext_rd_wait <= 1'b0;
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ext_wr_wait <= 1'b0;
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ext_access <= 1'b0; //empty
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ext_write <= 1'b0;
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ext_datamode[1:0] <= 2'b0;
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ext_ctrlmode[3:0] <= 4'b0;
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ext_data[31:0] <= 32'b0;
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ext_dstaddr[31:0] <= 32'b0;
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ext_srcaddr[31:0] <= 32'b0;
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ext_rd_wait <= 1'b0;
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ext_wr_wait <= 1'b0;
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stim_addr[MAW-1:0] <= 'd0;
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transaction[MW-1:0] <= 'd0;
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end
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else if (go & ~dut_wr_wait)
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//else if ((go & ~ext_access) | (go & ext_access & ~dut_wr_wait))
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begin
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ext_access <= 1'b1;
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ext_data[31:0] <= ext_data[31:0] + 32'b1;
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ext_dstaddr[31:0] <= ext_dstaddr[31:0] + 32'd8;//(32'b1<<datamode)
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ext_datamode[1:0] <= datamode[1:0];
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end
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`ifdef MANUAL
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transaction[MW-1:0] <= stimarray[stim_addr];
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ext_access <= transaction[0];
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ext_write <= transaction[1];
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ext_datamode[1:0] <= transaction[3:2];
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ext_ctrlmode[3:0] <= transaction[7:4];
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ext_dstaddr[31:0] <= transaction[39:8];
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ext_data[31:0] <= transaction[71:40];
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ext_srcaddr[31:0] <= transaction[103:72];
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stim_addr[MAW-1:0] <= stim_addr[MAW-1:0] + 1'b1;
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`else
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ext_access <= 1'b1;
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ext_data[31:0] <= ext_data[31:0] + 32'b1;
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ext_dstaddr[31:0] <= ext_dstaddr[31:0] + 32'd8;//(32'b1<<datamode)
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ext_datamode[1:0] <= datamode[1:0];
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`endif
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end
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//Waveform dump
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`ifndef TARGET_VERILATOR
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initial
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@ -1,10 +1,14 @@
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#!/bin/bash
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#Linting in Verilator
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verilator --lint-only -F elink.cmd -DTARGET_VERILATOR
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#verilator --lint-only -F elink.cmd -DTARGET_VERILATOR
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#Compiling sim
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iverilog -f elink.cmd
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#a sorry hack, too tired to get it right, please fix...
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TRANS=$(wc -l test.memh)
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TRANS=${TRANS:0:3}
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#RANDOM TEST
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iverilog -f elink.cmd -DMANUAL -DTRANS=$TRANS -DTESTNAME=test.memh
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#iverilog -f elink.cmd -DAUTO
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#Running sim
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./a.out
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