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Fix 0 day bug...

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- this shows why it's so important to read the warnings. (circuit was broken!)
This commit is contained in:
Andreas Olofsson 2015-11-09 13:21:26 -05:00
parent bf614a9873
commit 64f55eb792
2 changed files with 45 additions and 31 deletions
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29
common/hdl/dsync.v
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@ -15,27 +15,30 @@ module dsync (/*AUTOARG*/
`ifdef TARGET_SIM `ifdef TARGET_SIM
reg [PS-1:0] sync_pipe[DW-1:0]; reg [DW-1:0] sync_pipe[PS-1:0];
`else `else
(* ASYNC_REG = "TRUE" *) (* DONT_TOUCH = "TRUE" *) reg [PS-1:0] sync_pipe[DW-1:0]; (* ASYNC_REG = "TRUE" *) (* DONT_TOUCH = "TRUE" *) reg [DW-1:0] sync_pipe[PS-1:0];
`endif `endif
genvar i; genvar i;
integer j;
generate generate
for(i=0;i<DW;i=i+1) for(i=0;i<PS;i=i+1)
begin if(i==0)
always @ (posedge clk) begin
begin always @ (posedge clk)
sync_pipe[i][0] = din; sync_pipe[0][DW-1:0] <= din[DW-1:0];
for(j=1;j<PS;j=j+1) end
sync_pipe[i][j] = sync_pipe[i][j-1]; else
end begin
assign dout[i] = sync_pipe[i][PS-1]; always @ (posedge clk )
end sync_pipe[i][DW-1:0] <= sync_pipe[i-1][DW-1:0];
end // else: !if(i==0)
endgenerate endgenerate
assign dout[DW-1:0] = sync_pipe[PS-1][DW-1:0];
endmodule // dsync endmodule // dsync

41
common/hdl/rsync.v
View File

@ -16,28 +16,39 @@ module rsync (/*AUTOARG*/
//TOOD: Should only be one target //TOOD: Should only be one target
`ifdef TARGET_SIM `ifdef TARGET_SIM
reg [PS-1:0] sync_pipe[DW-1:0]; reg [DW-1:0] sync_pipe[PS-1:0];
`else `else
(* ASYNC_REG = "TRUE" *) (* DONT_TOUCH = "TRUE" *) reg [PS-1:0] sync_pipe[DW-1:0]; (* ASYNC_REG = "TRUE" *) (* DONT_TOUCH = "TRUE" *) reg [DW-1:0] sync_pipe[PS-1:0];
`endif `endif
genvar i; genvar i;
integer j; genvar j;
generate generate
for(i=0;i<DW;i=i+1) for(i=0;i<PS;i=i+1)
begin if(i==0)
always @ (posedge clk or negedge nrst_in[i]) begin
if(!nrst_in[i]) for(j=0;j<DW;j=j+1)
sync_pipe[i] <= 'b0;
else
begin begin
sync_pipe[i][0] =1'b1; always @ (posedge clk or negedge nrst_in[j])
for(j=1;j<PS;j=j+1) if(!nrst_in[j])
sync_pipe[i][j] = sync_pipe[i][j-1]; sync_pipe[0][j] <= 1'b0;
else
sync_pipe[0][j] <= 1'b1;
end end
assign nrst_out[i] = sync_pipe[i][PS-1]; end
end else
begin
for(j=0;j<DW;j=j+1)
begin
always @ (posedge clk or negedge nrst_in[j])
if(!nrst_in[j])
sync_pipe[i][j] <= 1'b0;
else
sync_pipe[i][j] <= sync_pipe[i-1][j];
end
end
endgenerate endgenerate
assign nrst_out[DW-1:0] = sync_pipe[PS-1][DW-1:0];
endmodule // rsync endmodule // rsync