Fix 0 day bug...

- this shows why it's so important to read the warnings. (circuit was broken!)

common/hdl/dsync.v

@@ -15,27 +15,30 @@ module dsync (/*AUTOARG*/
    
  
 `ifdef TARGET_SIM
-   reg [PS-1:0]    sync_pipe[DW-1:0];
+   reg [DW-1:0]    sync_pipe[PS-1:0];
 `else   
-   (* ASYNC_REG = "TRUE"  *) (* DONT_TOUCH =  "TRUE" *) reg [PS-1:0]    sync_pipe[DW-1:0];   
+   (* ASYNC_REG = "TRUE"  *) (* DONT_TOUCH =  "TRUE" *) reg [DW-1:0]    sync_pipe[PS-1:0];   
 `endif
    
    
    genvar 	i;
-   integer 	j;
 
-   generate
+   generate          
-      for(i=0;i<DW;i=i+1)
+      for(i=0;i<PS;i=i+1)
-	begin
+	if(i==0)
-	   always @ (posedge clk)
+	  begin
-	     begin
+	     always @ (posedge clk)
-		sync_pipe[i][0] = din;		  
+	       sync_pipe[0][DW-1:0] <= din[DW-1:0];	     
-		for(j=1;j<PS;j=j+1)
+	  end
-		  sync_pipe[i][j] = sync_pipe[i][j-1];		  
+	else
-	     end
+	  begin
-	   assign dout[i] = sync_pipe[i][PS-1];
+	  always @ (posedge clk )
-	end 
+	    sync_pipe[i][DW-1:0] <= sync_pipe[i-1][DW-1:0];	     
+	  end // else: !if(i==0)      
    endgenerate
    
+   assign dout[DW-1:0] = sync_pipe[PS-1][DW-1:0];
+ 
+   
 endmodule // dsync
 

common/hdl/rsync.v

@@ -16,28 +16,39 @@ module rsync (/*AUTOARG*/
    
    //TOOD: Should only be one target
 `ifdef TARGET_SIM
-   reg [PS-1:0]    sync_pipe[DW-1:0];
+   reg [DW-1:0]    sync_pipe[PS-1:0];
 `else   
-   (* ASYNC_REG = "TRUE"  *) (* DONT_TOUCH =  "TRUE" *) reg [PS-1:0]    sync_pipe[DW-1:0];   
+   (* ASYNC_REG = "TRUE"  *) (* DONT_TOUCH =  "TRUE" *) reg [DW-1:0]    sync_pipe[PS-1:0];   
 `endif
  
    genvar 	i;
-   integer 	j;
+   genvar 	j;   
-   
+   generate          
-   generate    
+      for(i=0;i<PS;i=i+1)
-      for(i=0;i<DW;i=i+1)
+	if(i==0)
-	begin
+	  begin
-	   always @ (posedge clk or negedge nrst_in[i])
+	     for(j=0;j<DW;j=j+1)		 
-	     if(!nrst_in[i])
-	       sync_pipe[i]  <= 'b0;
-	     else
 	       begin
-		  sync_pipe[i][0] =1'b1;		  
+		  always @ (posedge clk or negedge nrst_in[j])		 
-		  for(j=1;j<PS;j=j+1)
+		    if(!nrst_in[j])
-		    sync_pipe[i][j] = sync_pipe[i][j-1];		  
+		      sync_pipe[0][j] <= 1'b0;
+		    else
+		      sync_pipe[0][j] <= 1'b1;	     
 	       end
-	   assign nrst_out[i] = sync_pipe[i][PS-1];
+	  end
-	end      
+	else
+	  begin
+	     for(j=0;j<DW;j=j+1)		 
+	       begin
+		  always @ (posedge clk or negedge nrst_in[j])		 
+		    if(!nrst_in[j])
+		      sync_pipe[i][j] <= 1'b0;
+		    else
+		      sync_pipe[i][j] <=  sync_pipe[i-1][j]; 
+	       end
+	  end	  	 
    endgenerate
-
+   
+   assign nrst_out[DW-1:0] = sync_pipe[PS-1][DW-1:0];
+   		    	
 endmodule // rsync