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Added wait generator for fifo (experimental)

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- found it very difficult to get to some of the hard to reach scenarios
- the wait circuit helps generate fifo full
- off by default!
This commit is contained in:
Andreas Olofsson 2015-11-24 01:05:04 -05:00
parent 162cb022f9
commit 65708a2be9
2 changed files with 30 additions and 3 deletions
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31
memory/hdl/fifo_async.v
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@ -9,7 +9,8 @@ module fifo_async
parameter DW = 104; //FIFO width
parameter DEPTH = 32; //FIFO depth
parameter TYPE = "XILINX";//"BASIC" or "XILINX" or "ALTERA"
parameter WAIT = 1; //assert random prog_full wait
//##########
//# RESET/CLOCK
//##########
@ -33,6 +34,11 @@ module fifo_async
output empty;
output valid;
wire fifo_prog_full;
wire wait_random;
assign prog_full = fifo_prog_full | wait_random;
generate
if(TYPE=="BASIC") begin : basic
fifo_async_model
@ -42,7 +48,7 @@ if(TYPE=="BASIC") begin : basic
/*AUTOINST*/
// Outputs
.full (full),
.prog_full (prog_full),
.prog_full (fifo_prog_full),
.dout (dout[DW-1:0]),
.empty (empty),
.valid (valid),
@ -61,7 +67,7 @@ else if (TYPE=="XILINX") begin : xilinx
/*AUTOINST*/
// Outputs
.full (full),
.prog_full (prog_full),
.prog_full (fifo_prog_full),
.dout (dout[DW-1:0]),
.empty (empty),
.valid (valid),
@ -76,6 +82,25 @@ else if (TYPE=="XILINX") begin : xilinx
end // if ((DW==104) & (DEPTH==32))
end // block: xilinx
endgenerate
//Random wait generator
generate
if(WAIT)
begin
reg [7:0] wait_counter;
always @ (posedge wr_clk or posedge rst)
if(rst)
wait_counter[7:0] <= 'b0;
else
wait_counter[7:0] <= wait_counter+1'b1;
assign wait_random = (|wait_counter[4:0]);//(|wait_counter[3:0]);//1'b0;
end
else
begin
assign wait_random = 1'b0;
end // else: !if(WAIT)
endgenerate
endmodule // fifo_async
// Local Variables:

2
memory/hdl/fifo_cdc.v
View File

@ -13,6 +13,7 @@ module fifo_cdc (/*AUTOARG*/
parameter DW = 104;
parameter DEPTH = 32;
parameter WAIT = 0;
/********************************/
/*Shard async reset */
@ -60,6 +61,7 @@ module fifo_cdc (/*AUTOARG*/
//Read response fifo (from master)
defparam fifo.DW = DW;
defparam fifo.DEPTH = DEPTH;
defparam fifo.WAIT = WAIT;
fifo_async fifo (.prog_full (prog_full),//stay safe for now
.full (full),