FPGA/oh
1
0
Fork 0
mirror of https://github.com/aolofsson/oh.git synced 2025-02-07 06:44:09 +08:00
Code Issues Projects Releases Wiki Activity

Rewritten trace script for spike

Browse Source 
-ovpsim is a dead end, good bye
This commit is contained in:
Andreas.Olofsson 2020-03-28 15:37:10 -04:00
parent cbb8f79fd2
commit 65aa1b061c
1 changed files with 55 additions and 29 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

84
scripts/trace2trace
View File

@ -2,24 +2,24 @@
############################################################################# #############################################################################
# trace2trace <inputfile> <outputfile> # trace2trace <inputfile> <outputfile>
# #
# Converts a simulation trace file to the epiphany trace format # Converts a simulator trace file to the epiphany trace format
# #
# Simulators supported: ovpsim, spike # Formats: spike, cgen
# #
############################################################################# #############################################################################
import re import re
import sys import sys
simulator="spike"
offset=0xffffffff00000000
#Input Arguments #Input Arguments
with open(sys.argv[1], 'r') as f: with open(sys.argv[1], 'r') as f:
file_content = f.read() file_content = f.read()
fileout=open(sys.argv[2],"w") fileout=open(sys.argv[2],"w")
#Reading input file into buffer #RISC-V ABI dictionary
list=file_content.split('\'riscvOVPsim/cpu\'')
#ABI dictionary
regs={ regs={
"zero":"r0", "zero":"r0",
"ra":"r1", "ra":"r1",
@ -60,27 +60,53 @@ regs={
"mepc":"mepc", "mepc":"mepc",
"mcause":"mcause", "mcause":"mcause",
} }
#Format Trace
for i in list: #Reading input file into buffer
instr=i.replace('\n',' ') #replace all newlines in middle of strings if(simulator=="spike") :
instr=instr.replace('Info','') #remove info trap=0
instr=re.sub('\(SIGNATURE_DUMP.*','',instr) #remove crud from end of file list=file_content.split('core 0: ') #split based on core 0
if(re.search('^\,',instr)) : #filter out more crud for i in list:
fields=instr.split() #split into fields i=re.sub(r'\n', ' ', i) #combine lines
pc=re.sub('\(.*','',fields[1]) i=re.sub(r'x (\d{1})',r'x\1', i) #fix brain dead spike print for regs
pc=re.sub('0x','',pc) #removing hex prefix i=re.sub(r'^0x0000000000001(.*)',r'', i) #remove spike boot rom
opcode=fields[2] if(bool(re.search('trap_user_ecall',i))):#filter out everything after ecall
name=fields[3].rjust(8) trap=1
if(re.search('\-\>',instr)) : #filter empty instructions
#print("XXX" + instr) if((bool(re.search('0x',i))) & (trap==0)):
reg=fields[-4] fields=i.split()
reg=regs[reg] pc=int(fields[0],16)
val=fields[-1] opcode=fields[1]
if(re.search('^r',reg)) : asm=fields[2]
update=reg + "=" + val.zfill(16); #don't update csrs for now #for j in fields:
else : # print (j)
update="" if(re.search('0x',fields[-2])):
fileout.write("TRACE: cpu_0.trace PC=" + pc + " I=" + name + " F=-------- " + update + "\n") memaddr="--"
memdata="--"
reg="--"
regdata="--"
elif(re.search('mem',i)):
memaddr=fields[-2]
memdata=fields[-1]
reg="--"
regdata="--"
else:
reg="x{0:02}".format(int(re.sub(r'x',r'', fields[-2])))
regdata=fields[-1]
memaddr="--"
memdata="--"
#Remove offsets
if(pc>=offset):
pc=pc-offset
#List of entires
flist=["0x{0:08x}".format(pc),
opcode,
"{:<8}".format(asm),
"{:<3}".format(reg),
"{:<10}".format(regdata),
"{:<10}".format(memaddr),
"{:<10}".format(memdata)]
outputstring=' , '.join(flist)
fileout.write(outputstring + "\n")
fileout.close() fileout.close()