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Fixing careless mistakes..

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This commit is contained in:
Andreas Olofsson 2015-11-06 22:51:09 -05:00
parent 9383f32764
commit 65f772ddef
5 changed files with 84 additions and 84 deletions
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2
elink/hdl/elink.v
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@ -153,7 +153,6 @@ module elink (/*AUTOARG*/
*/ */
defparam erx.ID = ID; defparam erx.ID = ID;
defparam erx.IOSTD_ELINK = IOSTD_ELINK;
defparam erx.ETYPE = ETYPE; defparam erx.ETYPE = ETYPE;
erx erx(.rx_active (elink_active), erx erx(.rx_active (elink_active),
@ -205,7 +204,6 @@ module elink (/*AUTOARG*/
*/ */
defparam etx.ID = ID; defparam etx.ID = ID;
defparam etx.IOSTD_ELINK = IOSTD_ELINK;
defparam etx.ETYPE = ETYPE; defparam etx.ETYPE = ETYPE;
etx etx(.etx_nreset (etx_nreset), etx etx(.etx_nreset (etx_nreset),

5
elink/hdl/erx.v
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@ -106,9 +106,8 @@ module erx (/*AUTOARG*/
/***********************************************************/ /***********************************************************/
/*RECEIVER I/O LOGIC */ /*RECEIVER I/O LOGIC */
/***********************************************************/ /***********************************************************/
defparam erx_io.IOSTD_ELINK=IOSTD_ELINK; erx_io #(.ETYPE(ETYPE))
defparam erx_io.ETYPE=ETYPE; erx_io (
erx_io erx_io (
/*AUTOINST*/ /*AUTOINST*/
// Outputs // Outputs
.rx_clkin (rx_clkin), .rx_clkin (rx_clkin),

28
elink/hdl/erx_clocks.v
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@ -103,28 +103,28 @@ module erx_clocks (/*AUTOARG*/
always @ (posedge sys_clk or negedge rx_nreset_in) always @ (posedge sys_clk or negedge rx_nreset_in)
if(!rx_nreset_in) if(!rx_nreset_in)
reset_state[2:0] <= `RESET_ALL; reset_state[2:0] <= `RX_RESET_ALL;
else if(heartbeat) else if(heartbeat)
case(reset_state[2:0]) case(reset_state[2:0])
`RESET_ALL : `RX_RESET_ALL :
if(~soft_reset) if(~soft_reset)
reset_state[2:0] <= `START_PLL; reset_state[2:0] <= `RX_START_PLL;
`START_PLL : `RX_START_PLL :
if(pll_locked_sync & idelay_ready) if(pll_locked_sync & idelay_ready)
reset_state[2:0] <= `ACTIVE; reset_state[2:0] <= `RX_ACTIVE;
`ACTIVE: `RX_ACTIVE:
if(soft_reset) if(soft_reset)
reset_state[2:0] <= `RESET_ALL; //stay there until next reset reset_state[2:0] <= `RX_RESET_ALL; //stay there until next reset
endcase // case (reset_state[2:0]) endcase // case (reset_state[2:0])
assign pll_reset = (reset_state[2:0]==`RESET_ALL); assign pll_reset = (reset_state[2:0]==`RX_RESET_ALL);
assign idelay_reset = (reset_state[2:0]==`RESET_ALL); assign idelay_reset = (reset_state[2:0]==`RX_RESET_ALL);
//asynch rx block reset //asynch rx block reset
assign rx_nreset = ~(reset_state[2:0] != `ACTIVE); assign rx_nreset = ~(reset_state[2:0] != `RX_ACTIVE);
//active indicator //active indicator
assign rx_active = (reset_state[2:0] == `ACTIVE); assign rx_active = (reset_state[2:0] == `RX_ACTIVE);
//############################# //#############################
//#RESET SYNCING //#RESET SYNCING
@ -133,13 +133,15 @@ module erx_clocks (/*AUTOARG*/
.nrst_out (erx_io_nreset), .nrst_out (erx_io_nreset),
// Inputs // Inputs
.clk (rx_lclk), .clk (rx_lclk),
.nrst_in (rx_nreset)); .nrst_in (rx_nreset)
);
rsync rsync_core (// Outputs rsync rsync_core (// Outputs
.nrst_out (erx_nreset), .nrst_out (erx_nreset),
// Inputs // Inputs
.clk (rx_lclk_div4), .clk (rx_lclk_div4),
.nrst_in (rx_nreset)); .nrst_in (rx_nreset)
);
`ifdef TARGET_XILINX `ifdef TARGET_XILINX

3
elink/hdl/etx.v
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@ -182,7 +182,8 @@ module etx(/*AUTOARG*/
/*TRANSMIT I/O LOGIC */ /*TRANSMIT I/O LOGIC */
/***********************************************************/ /***********************************************************/
etx_io etx_io (.nreset (etx_io_nreset), etx_io #(.ETYPE(ETYPE))
etx_io (.nreset (etx_io_nreset),
/*AUTOINST*/ /*AUTOINST*/
// Outputs // Outputs
.txo_lclk_p (txo_lclk_p), .txo_lclk_p (txo_lclk_p),

42
elink/hdl/etx_clocks.v
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@ -110,44 +110,44 @@ module etx_clocks (/*AUTOARG*/
//Reset sequence state machine //Reset sequence state machine
always @ (posedge sys_clk or negedge sys_nreset) always @ (posedge sys_clk or negedge sys_nreset)
if(!sys_nreset) if(!sys_nreset)
reset_state[2:0] <= `RESET_ALL; reset_state[2:0] <= `TX_RESET_ALL;
else if(heartbeat) else if(heartbeat)
case(reset_state[2:0]) case(reset_state[2:0])
`RESET_ALL : `TX_RESET_ALL :
if(~soft_reset) if(~soft_reset)
reset_state[2:0] <= `START_CCLK; reset_state[2:0] <= `TX_START_CCLK;
`START_CCLK : `TX_START_CCLK :
if(mmcm_locked_sync) if(mmcm_locked_sync)
reset_state[2:0] <= `STOP_CCLK; reset_state[2:0] <= `TX_STOP_CCLK;
`STOP_CCLK : `TX_STOP_CCLK :
reset_state[2:0] <= `DEASSERT_RESET; reset_state[2:0] <= `TX_DEASSERT_RESET;
`DEASSERT_RESET : `TX_DEASSERT_RESET :
reset_state[2:0] <= `HOLD_IT; reset_state[2:0] <= `TX_HOLD_IT;
`HOLD_IT : `TX_HOLD_IT :
if(mmcm_locked_sync) if(mmcm_locked_sync)
reset_state[2:0] <= `ACTIVE; reset_state[2:0] <= `TX_ACTIVE;
`ACTIVE: `TX_ACTIVE:
if(soft_reset) if(soft_reset)
reset_state[2:0] <= `RESET_ALL; //stay there until nex reset reset_state[2:0] <= `TX_RESET_ALL; //stay there until nex reset
endcase // case (reset_state[2:0]) endcase // case (reset_state[2:0])
//reset mmcm (async) //reset mmcm (async)
assign mmcm_reset = (reset_state[2:0]==`RESET_ALL) | assign mmcm_reset = (reset_state[2:0]==`TX_RESET_ALL) |
(reset_state[2:0]==`STOP_CCLK) | (reset_state[2:0]==`TX_STOP_CCLK) |
(reset_state[2:0]==`DEASSERT_RESET) (reset_state[2:0]==`TX_DEASSERT_RESET)
; ;
//reset chip (active low) //reset chip (active low)
assign chip_nreset = (reset_state[2:0]==`DEASSERT_RESET) | assign chip_nreset = (reset_state[2:0]==`TX_DEASSERT_RESET) |
(reset_state[2:0]==`HOLD_IT) | (reset_state[2:0]==`TX_HOLD_IT) |
(reset_state[2:0]==`ACTIVE); (reset_state[2:0]==`TX_ACTIVE);
//reset the elink //reset the elink
assign tx_nreset = ~(reset_state[2:0] != `ACTIVE); assign tx_nreset = ~(reset_state[2:0] != `TX_ACTIVE);
assign tx_active = (reset_state[2:0] == `ACTIVE); assign tx_active = (reset_state[2:0] == `TX_ACTIVE);
//############################# //#############################
//#RESET SYNCING //#RESET SYNCING