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@ -13,7 +13,7 @@ Chip Design Glossary
* [DDS](https://en.wikipedia.org/wiki/Direct_digital_synthesizer): Direct digital synthesis
* [DSP](https://en.wikipedia.org/wiki/Digital_signal_processor): Digital signal processor
* [Ethernet](https://en.wikipedia.org/wiki/Ethernet): Family of standard network technologies
* [FPGA](https://en.wikipedia.org/wiki/Field-programmable_gate_array): Field-programmable gate array (FPGA) is an integrated circuit designed to be configured by a customer or a designer after manufacturing.
* [FPGA](https://en.wikipedia.org/wiki/Field-programmable_gate_array): Field-programmable gate array is a chip that can be reprogrammed "in the field".
* [FIFO](https://en.wikipedia.org/wiki/FIFO_%28computing_and_electronics%29): First in first out buffer
* [DRAM](https://en.wikipedia.org/wiki/Dynamic_random-access_memory): Dynamic random-access semiconductor memory
* [Flash](https://en.wikipedia.org/wiki/Flash_memory): Non-volatile semiconductor memory
@ -21,7 +21,7 @@ Chip Design Glossary
* [GPIO](https://en.wikipedia.org/wiki/General-purpose_input/output): IO controllale at run time
* [Gray code](https://en.wikipedia.org/wiki/Gray_code): Binary system where successive values differ by one bit
* [I2C](https://en.wikipedia.org/wiki/I%C2%B2C): Multi-master 2 wire bus
* [LVDS}(https://en.wikipedia.org/wiki/Low-voltage_differential_signaling): Low-voltage differential signaling (also TIA/EIA-644)
* [LVDS](https://en.wikipedia.org/wiki/Low-voltage_differential_signaling): Low-voltage differential signaling (also TIA/EIA-644)
* [MUX](https://en.wikipedia.org/wiki/Multiplexer): Multiplexer
* [Multiplier](https://en.wikipedia.org/wiki/Binary_multiplier): Binary multiplier
* [NCO](https://en.wikipedia.org/wiki/Numerically_controlled_oscillator): Numerically controlled oscillator
@ -44,53 +44,51 @@ Chip Design Glossary
* [Antenna effect](https://en.wikipedia.org/wiki/Antenna_effect): Plasma induced gate oxide damage that can occur during semiconductor processing.
* [BIST](https://en.wikipedia.org/wiki/Built-in_self-test): Built in Self Test
* [Chip](https://en.wikipedia.org/wiki/Integrated_circuit): A set of electronic circuits on one small plate ("chip") of semiconductor material, normally silicon.
* [Clock gating](https://en.wikipedia.org/wiki/Clock_gating): Technique to save power in synchronous logic design. Dynamically shuts off unused portions of the clock tree.
* [Clock gating](https://en.wikipedia.org/wiki/Clock_gating): Technique whereby clock in synchronous logic is shut off when idle.
* [CMOS](https://en.wikipedia.org/wiki/CMOS): Complimentary metal-oxide semiconductor
* [Cross talk](https://en.wikipedia.org/wiki/Crosstalk): The coupling of nearby signals on a chip, usually through capacitive coupling.
* [DEF](https://en.wikipedia.org/wiki/Design_Exchange_Format): Design Exchange Format for layout
* [DFM](https://en.wikipedia.org/wiki/Design_for_manufacturability): Extended DRC rules specifying how to make a high yielding design.
* [DFT](https://en.wikipedia.org/wiki/Design_for_testing): Design for Test
* [Die](https://en.wikipedia.org/wiki/Die_%28integrated_circuit%29): Small block of semiconductor material that can be cut ("diced") from a silicon wafer
* [DRC](https://en.wikipedia.org/wiki/Design_rule_checking): Design Rule Constraints specifying manufacturing constraints
* [DV](https://en.wikipedia.org/wiki/Functional_verification): Design Verification (DV) is the process of verifying that the logic design conforms to specification.
* [DFT](https://en.wikipedia.org/wiki/Design_for_testing): Design for test
* [Die](https://en.wikipedia.org/wiki/Die_%28integrated_circuit%29): Small block of semiconductor material that can be cut ("diced") from a silicon wafer.
* [DRC](https://en.wikipedia.org/wiki/Design_rule_checking): Design Rule Constraints specifying manufacturing constraints.
* [DV](https://en.wikipedia.org/wiki/Functional_verification): Design verification is the process of verifying that the logic design conforms to specification.
* [EDA](https://en.wikipedia.org/wiki/Electronic_design_automation): Electronic Design Automation tools used to enhance chip design productivity.
* [Electromigration](https://en.wikipedia.org/wiki/Electromigration): Transport of material caused by the gradual movement of the ions in a conductor due to the momentum transfer between conducting electrons and diffusing metal atoms.
* [EMI](https://en.wikipedia.org/wiki/Electromagnetic_interference): Electromagnetic interference
* [ESD](https://en.wikipedia.org/wiki/Electrostatic_discharge): Electrostatic discharge (ESD) is the sudden flow of electricity between two electrically charged objects caused by contact, an electrical short, or dielectric breakdown.
* [Fabless](https://en.wikipedia.org/wiki/Fabless_manufacturing): The design and sale of semiconductor devices while outsourcing the manufacturing (fabrication) to 3rd party semiconductor foundries.
* [Electromigration](https://en.wikipedia.org/wiki/Electromigration): Transport of material caused by the gradual movement of the ions in a conductor.
* [EMI](https://en.wikipedia.org/wiki/Electromagnetic_interference): Electromagnetic interference.
* [ESD](https://en.wikipedia.org/wiki/Electrostatic_discharge): Electrostatic discharge is the sudden flow of electricity between two electrically charged objects.
* [Fabless](https://en.wikipedia.org/wiki/Fabless_manufacturing): The design and sale of semiconductor devices while outsourcing the manufacturing to 3rd party.
* [FEOL](https://en.wikipedia.org/wiki/Front_end_of_line): Front end of line processing. Includes all chop processing up to but not including metal interconnect layers.
* [Flip-flop](https://en.wikipedia.org/wiki/Flip-flop_(electronics)): A clocked circuit that has two stable states and can be used to store state information. Usually understood to be clock edge sensitive.
* [Foundry](https://en.wikipedia.org/wiki/Semiconductor_fabrication_plant): Semiconductor company offering manufacturing services
* [GDSII](https://en.wikipedia.org/wiki/GDSII): Binary format of design database sent to foundry
* [Flip-flop](https://en.wikipedia.org/wiki/Flip-flop_(electronics)): A clocked circuit that has two stable states and can be used to store state information.
* [Foundry](https://en.wikipedia.org/wiki/Semiconductor_fabrication_plant): Semiconductor company offering manufacturing services.
* [GDSII](https://en.wikipedia.org/wiki/GDSII): Binary format of design database sent to foundry.
* [HDL](https://en.wikipedia.org/wiki/Hardware_description_language): Specialized hardware description lanaguage for describing electronic circuits.
* [IP](https://en.wikipedia.org/wiki/Semiconductor_intellectual_property_core): Semiconductor reusable design blocks containing author's Intellectual Property. Can be licensed under open source or commercial terms.
* [IP Vendors](https://en.wikipedia.org/wiki/List_of_semiconductor_IP_core_vendors): List of commercial semiconductor IP vendors
* [IP](https://en.wikipedia.org/wiki/Semiconductor_intellectual_property_core): Semiconductor reusable design blocks containing author's Intellectual Property.
* [IP Vendors](https://en.wikipedia.org/wiki/List_of_semiconductor_IP_core_vendors): List of commercial semiconductor IP vendors.
* [Jitter](https://en.wikipedia.org/wiki/Jitter): Deviation from perfect periodicity.
* [Latchup](https://en.wikipedia.org/wiki/Latch-up):A type of short circuit that can occur in a chip due to inadvertent creation of a low-impedance path between the power supply rails of a MOSFET circuit, triggering a parasitic structure which disrupts proper functioning of the part.
* [Layout](https://en.wikipedia.org/wiki/Integrated_circuit_layout): Representation of an integrated circuit in terms of planar geometric shapes which correspond to the patterns of metal, oxide, or semiconductor layers that make up the components of the integrated circuit.
* [LEF](https://en.wikipedia.org/wiki/Library_Exchange_Format): Standard Cell Library Exchange Format layout
* [Logical Effort](https://en.wikipedia.org/wiki/Logical_effort): Term coined by Ivan Sutherland and Bob Sproull as a straightforward technique used to normalize delays in a circuit.
* [Latchup](https://en.wikipedia.org/wiki/Latch-up): Short circuit due to inadvertent creation of a low-impedance path between the power supply rails of a MOSFET circuit.
* [Layout](https://en.wikipedia.org/wiki/Integrated_circuit_layout): Physical representation of an integrated circuit.
* [LEF](https://en.wikipedia.org/wiki/Library_Exchange_Format): Standard Cell Library Exchange Format layout.
* [Logical Effort](https://en.wikipedia.org/wiki/Logical_effort): Technique used to normalize (and optimize) digital circuits speed paths.
* [LVS](https://en.wikipedia.org/wiki/Layout_Versus_Schematic): Layout Versus Schematic software checks that the layout is identical to the netlist.
* [Mask Works](https://en.wikipedia.org/wiki/Integrated_circuit_layout_design_protection): A special field of US intellectual properly law dedicated to 2D and 3D integrated circuit "layouts".
* [Mask Works](https://en.wikipedia.org/wiki/Integrated_circuit_layout_design_protection): Copyright law dedicated to 2D and 3D integrated circuit "layouts".
* [MLS](https://en.wikipedia.org/wiki/Moisture_sensitivity_level): Packaging and handling precautions for some semiconductors.
* [Moore's Law](https://en.wikipedia.org/wiki/Moore%27s_law): Observation by Gordon Moore that the number of transistors in an IC doubles approximately every two years.
* [MOSIS](https://en.wikipedia.org/wiki/MOSIS): Foundry service project offering MPW and low volume manufacturing. Jointly funded by DARPA and NSF in 1986 and still active today.
* [MPW](https://en.wikipedia.org/wiki/Multi-project_wafer_service): Multi-project wafer service that integrates multiple designs on one reticle. Also referred to as a shuttle.
* [Multi-threshold CMOS](https://en.wikipedia.org/wiki/Multi-threshold_CMOS): Variation of CMOS technology with multiple threshold voltages to offer designer more options for meeting power and performance targets.
* [Optical proximity correction](https://en.wikipedia.org/wiki/Optical_proximity_correction): Photo-lithography enhancement technique used to compensate for image errors due to diffraction or process effects in semiconductor manufacturing.
* [PDK](https://en.wikipedia.org/wiki/Process_design_kit): Process design kits consist of a set of files that typically contain descriptions of the basic building blocks of the process.
* [MOSIS](https://en.wikipedia.org/wiki/MOSIS): Foundry service project offering MPWs and low volume manufacturing.
* [MPW](https://en.wikipedia.org/wiki/Multi-project_wafer_service): Multi-project wafer service that integrates multiple designs on one reticle (aka "shuttle").
* [Multi-threshold CMOS](https://en.wikipedia.org/wiki/Multi-threshold_CMOS): CMOS technology with multiple transistor types with different threshold voltages.
* [Optical proximity correction](https://en.wikipedia.org/wiki/Optical_proximity_correction): Technique used to compensate for semiconductor diffraction/process effects.
* [PDK](https://en.wikipedia.org/wiki/Process_design_kit): Process design kits consist of a set of minimum set of files needed to design in a specific process.
* [Power gating](https://en.wikipedia.org/wiki/Power_gating): Technique used to reduce leakage/standby power by shutting of the supply to the circuit.
* [P&R](https://en.wikipedia.org/wiki/Place_and_route): Automated Place and Route of a circuit using an EDA tool
* [PVT Corners](https://en.wikipedia.org/wiki/Process_corners): Represents the extremes of the process, voltage, and temperature that could likely occur in a given semiconductor process. Can include combinations of FEOL (NMOS/PMOS) and BEOL, temperature (eg -40-->125 deg), and voltage (eg nominal +/- 10%).
* [RTL](https://en.wikipedia.org/wiki/Register-transfer_level): Design abstraction which models digital circuit as storage registers and logical operations on the values of those registers.
* [SEU](https://en.wikipedia.org/wiki/Single_event_upset): Change of state caused by one single ionizing particle (ions, electrons, photons...) striking a sensitive node in a micro-electronic device
* [Signoff](https://en.wikipedia.org/wiki/Signoff_%28electronic_design_automation%29): The final stamp of approval that the design is ready to be sent to foundry for manufacturing.
* [PVT Corners](https://en.wikipedia.org/wiki/Process_corners): Represents the extreme process, voltage, temperature that could occur in a given semiconductor process.
* [RTL](https://en.wikipedia.org/wiki/Register-transfer_level): Design abstraction for digital circuit design
* [SEU](https://en.wikipedia.org/wiki/Single_event_upset): Change of state caused by one single ionizing particle (ions, electrons, photons...).
* [Signoff](https://en.wikipedia.org/wiki/Signoff_%28electronic_design_automation%29): The final approval that the design is ready to be sent to foundry for manufacturing.
* [SOC](https://en.wikipedia.org/wiki/System_on_a_chip): System On Chip
* [Spice](https://en.wikipedia.org/wiki/SPICE): Open source analog electronic circuit simulator
* [STA](https://en.wikipedia.org/wiki/Static_timing_analysis): Method of computing the expected timing of a digital circuit without requiring a simulation of the full circuit.
* [Standard Cell Design](https://en.wikipedia.org/wiki/Standard_cell): The process of designing chips using fixed standard cell libraries. Design process only involves placing standard cells and routing them together using M1 and above.
* [STA](https://en.wikipedia.org/wiki/Static_timing_analysis): Method of computing the expected timing of a digital circuit without requiring full circuit simulation.
* [Standard Cell Design](https://en.wikipedia.org/wiki/Standard_cell): Design process relying on a fixed set of standard cells.
* [Synthesis](https://en.wikipedia.org/wiki/Logic_synthesis): Translation of high level design description (eg Verilog) to a netlist format (eg standard cell gate level)
* [SystemC](https://en.wikipedia.org/wiki/SystemC): Set of C+ class and macros for simulation. Commonly used for high level modeling and testing
* [Tape-out](https://en.wikipedia.org/wiki/Tape-out): Act of sending photomask chip database ("layout") to the manufacturer.
@ -100,35 +98,35 @@ Chip Design Glossary
## Manufacturing
* [Back grinding](https://en.wikipedia.org/wiki/Wafer_backgrinding): Wafer thickness is reduced to allow for stacking and high density packaging. Also referred to as "wafer thinning".
* [BEOL](https://en.wikipedia.org/wiki/Back_end_of_line): Back end of line processing for connecting together devices using metal interconnects.
* [Dicing](https://en.wikipedia.org/wiki/CMOS): Act of cutting up wafer into individual dies
* [FinFet](https://en.wikipedia.org/wiki/Multigate_device): Non planar, double-gate transistor.
* [Photo-lithography](https://en.wikipedia.org/wiki/Photolithography): Process used in micro-fabrication to pattern parts of a thin film or the bulk of a substrate.
* [Photomasks](https://en.wikipedia.org/wiki/Photomask): Opaque plates with holes or transparencies that allow light to shine through in a defined pattern.
* [Reticle](https://en.wikipedia.org/wiki/Photomask): A set of photomasks used by a stepper to step and print patterns onto a silicon wafer.
* [Semiconductor Fabrication](https://en.wikipedia.org/wiki/Semiconductor_device_fabrication): Process used to create the integrated circuits that are present in everyday electrical and electronic devices.
* [Silicon](https://en.wikipedia.org/wiki/Silicon): Chemical element (Si) forming the basis of the electronic revolution of the last 50 years. The eighth most common element in the universe by mass.
* [Silicon on insulator](https://en.wikipedia.org/wiki/Silicon_on_insulator): Layered silicon–insulator–silicon substrate in place to reduce parasitic device capacitance, thereby improving performance.
* [Semiconductor Fabrication](https://en.wikipedia.org/wiki/Semiconductor_device_fabrication): Process used to create the integrated circuits
* [Silicon](https://en.wikipedia.org/wiki/Silicon): Element (Si) forms the basis of the electronic revolution.
* [Silicon on insulator](https://en.wikipedia.org/wiki/Silicon_on_insulator): Layered silicon–insulator–silicon substrate in place to reduce parasitic device capacitance.
* [Stepper](https://en.wikipedia.org/wiki/Stepper): Machine that passes light through reticle onto the silicon wafer being processed.
* [TSV](https://en.wikipedia.org/wiki/Through-silicon_via): Vertical electrical connection (via) passing completely through a silicon wafer or die.
* [Wafer](https://en.wikipedia.org/wiki/Wafer_(electronics)): Thin slice of semiconductor material used in electronics for the fabrication of integrated circuits.
* [Wafer thinning](https://en.wikipedia.org/wiki/Wafer_backgrinding): Wafer thickness is reduced to allow for stacking and high density packaging.
## Packaging
* [3D IC's](https://en.wikipedia.org/wiki/Three-dimensional_integrated_circuit): The process of stacking integrated circuits and connecting them through TSVs.
All entries backed up by neutral Wiki entries.
* [BGA](https://en.wikipedia.org/wiki/Ball_grid_array): Ball grid array (BGA) is a type of surface-mount packaging (a chip carrier) used for integrated circuits.
* [BGA](https://en.wikipedia.org/wiki/Ball_grid_array): Ball grid array is a type of surface-mount packaging (a chip carrier) used for integrated circuits.
* [BGA substrate](https://en.wikipedia.org/wiki/Ball_grid_array): A miniaturized PCB that mates the silicon die to BGA pins.
* [Bumping](https://en.wikipedia.org/wiki/Flip_chip): Placing of bumps on wafer/dies in preparation for package assembly
* [Flip-chip](https://en.wikipedia.org/wiki/Flip_chip): Method of bonding a silicon die to package using solder bumps
* [IC Assembly](https://en.wikipedia.org/wiki/Integrated_circuit_packaging): Semiconductor die is encased in a supporting case "package".
* [Interposer](https://en.wikipedia.org/wiki/Interposer): Electrical interface used to spread a connection to a wider pitch. Can be based on silicon, ceramic, or organic material.
* [Interposer](https://en.wikipedia.org/wiki/Interposer): Electrical interface used to spread a connection to a wider pitch.
* [KGD](https://en.wikipedia.org/wiki/Wafer_testing): Known Good Die. Dies that have been completely tested at wafer probe.
* [Leadframe](https://en.wikipedia.org/wiki/Lead_frame): Metal structure inside a chip package that carry signals from the die to the outside. The die is glued to the leadframe and bond wires attach to the die pads.
* [Leadframe](https://en.wikipedia.org/wiki/Lead_frame): Metal structure inside a chip package that carry signals from the die to the outside.
* [POP](https://en.wikipedia.org/wiki/Package_on_package): Package on Package
* [SIP](https://en.wikipedia.org/wiki/System_in_package): System In Package
* [SMT](https://en.wikipedia.org/wiki/Surface-mount_technology): Surface mount technology(SMT) is a system assembly method whereby the pacakaged chips are mounted directly onto the PCB surface.
* [SMT](https://en.wikipedia.org/wiki/Surface-mount_technology): Technique whereby packaged chips are mounted directly onto the PCB surface.
* [Wirebond](https://en.wikipedia.org/wiki/Wire_bonding): Method of bonding a silicon die to a package using wires
* [WSI](https://en.wikipedia.org/wiki/Wafer-scale_integration): Wafer scale integration
@ -137,11 +135,10 @@ All entries backed up by neutral Wiki entries.
* [Arbitrary Waveform Generator](https://en.wikipedia.org/wiki/Arbitrary_waveform_generator): Electronic instrument used to generate arbitrary signal waveforms.
* [ATE](https://en.wikipedia.org/wiki/Automatic_test_equipment): Automatic Test Equipment for testing integrated circuits
* [Burn-in](https://en.wikipedia.org/wiki/Burn-in): Process of screening parts for potential premature life time failures.
Chip Design Glossary
* [DIB](https://en.wikipedia.org/wiki/DUT_board): Device Interface Board for interfacng DUT to ATE. Also called DUT board, probe card, load board, PIB.
* [DMM](https://en.wikipedia.org/wiki/Multimeter): Electronic instrument for measuring voltage, current, and resistance.
* [DUT](https://en.wikipedia.org/wiki/Device_under_test): Device under test
* [JTAG](https://en.wikipedia.org/wiki/Joint_Test_Action_Group): Industry standard for verifying and testing printed circuit boards after manufacturing. Also commonly used as a debug channel.
* [JTAG](https://en.wikipedia.org/wiki/Joint_Test_Action_Group): Industry standard for verifying and testing/debugging printed circuit boards after manufacturing.
* [Logic Analyzer](https://en.wikipedia.org/wiki/Logic_analyzer): Electronic instrument for capturing multiple digital signal from a system.
* [MCM](https://en.wikipedia.org/wiki/Multi-chip_module): Multi-chip Module
* [Oscilloscope](https://en.wikipedia.org/wiki/Oscilloscope): Electronic instrument for tracking the change of an electrical signal over time.