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https://github.com/aolofsson/oh.git
synced 2025-01-30 02:32:53 +08:00
Fixed burst tail bug
- Clearing the "done" register with tx_burst. Kind of makes sense logically since while we are in burst mode we are not done. - Still not 100% happy with this circuit, but there arent' a lot of lines of code left... - But elink now passes 500 random burst transactions!!!
This commit is contained in:
Andreas Olofsson
parent
5698302e05
commit
673fba168d
@ -13,15 +13,14 @@ module erx_clocks (/*AUTOARG*/
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`endif
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//Frequency Settings (Mhz)
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parameter FREQ_SYSCLK = 100;
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parameter FREQ_RXCLK = 300;
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parameter FREQ_RXCLK = 200;
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parameter FREQ_IDELAY = 200;
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parameter RXCLK_PHASE = 0; //270; //-90 deg rxclk phase shift
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parameter PLL_VCO_MULT = 4; //RX
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//Don't touch these! (derived parameters)
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localparam real RXCLK_PERIOD = 1000.000000/FREQ_RXCLK;
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localparam integer IREF_DIVIDE = PLL_VCO_MULT * FREQ_RXCLK/FREQ_IDELAY;
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localparam real RXCLK_PERIOD = 1000.000000 / FREQ_RXCLK;
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localparam integer IREF_DIVIDE = PLL_VCO_MULT * FREQ_RXCLK / FREQ_IDELAY;
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localparam integer RXCLK_DIVIDE = PLL_VCO_MULT; //1:1
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//Input clock, reset, config interface
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@ -42,8 +41,7 @@ module erx_clocks (/*AUTOARG*/
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output rx_active; // rx active
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output erx_nreset; // reset for rx core logic
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output erx_io_nreset; // io reset (synced to high speed clock)
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//############
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//# WIRES
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//############
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@ -83,15 +81,13 @@ module erx_clocks (/*AUTOARG*/
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reset_counter[RCW-1:0] <= reset_counter[RCW-1:0]+1'b1;
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heartbeat <= ~(|reset_counter[RCW-1:0]);
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end
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`define RX_RESET_ALL 3'b000
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`define RX_START_PLL 3'b001
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`define RX_ACTIVE 3'b010
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//Reset sequence state machine
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always @ (posedge sys_clk or negedge rx_nreset_in)
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if(!rx_nreset_in)
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reset_state[2:0] <= `RX_RESET_ALL;
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@ -15,14 +15,14 @@ module etx_clocks (/*AUTOARG*/
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//Frequency Settings (Mhz)
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parameter FREQ_SYSCLK = 100;
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parameter FREQ_TXCLK = 300;
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parameter FREQ_CCLK = 600;
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parameter FREQ_TXCLK = 100;
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parameter FREQ_CCLK = 400;
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parameter TXCLK_PHASE = 90; //txclk phase shift
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//Don't touch these! (derived parameters)
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localparam real SYSCLK_PERIOD = 1000.000000/FREQ_SYSCLK;
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localparam integer TXCLK_DIVIDE = MMCM_VCO_MULT*FREQ_SYSCLK/FREQ_TXCLK;
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localparam integer CCLK_DIVIDE = MMCM_VCO_MULT*FREQ_SYSCLK/FREQ_CCLK;
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localparam real SYSCLK_PERIOD = 1000.000000 / FREQ_SYSCLK;
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localparam integer TXCLK_DIVIDE = MMCM_VCO_MULT * FREQ_SYSCLK / FREQ_TXCLK;
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localparam integer CCLK_DIVIDE = MMCM_VCO_MULT * FREQ_SYSCLK / FREQ_CCLK;
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//VCO multiplers
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parameter MMCM_VCO_MULT = 12; //TX + CCLK
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@ -64,7 +64,6 @@ module etx_io (/*AUTOARG*/
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wire txo_lclk90;
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wire tx_new_frame;
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wire tx_lclk90_ddr;
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wire tx_wr_wait_async;
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wire tx_rd_wait_async;
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wire firstedge;
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@ -101,12 +100,6 @@ module etx_io (/*AUTOARG*/
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if(firstedge & ~tx_wait & ~(~tx_burst_reg & tx_state[2:0]==`CYCLE3))
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tx_packet_reg[PW-1:0] <= tx_packet[PW-1:0];
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//#########################################
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//# Transmit state machine
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//#########################################
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//decode incoming packet
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packet2emesh p2e_reg (
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.write_out (write),
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@ -116,9 +109,10 @@ module etx_io (/*AUTOARG*/
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.data_out (data[31:0]),
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.srcaddr_out (srcaddr[31:0]),
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.packet_in (tx_packet_reg[PW-1:0]));
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assign tx_new_frame = (tx_state[2:0]==`CYCLE1);
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//#########################################
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//# Transmit state machine
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//#########################################
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always @ (posedge tx_lclk_io)
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if(!nreset)
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@ -132,13 +126,16 @@ module etx_io (/*AUTOARG*/
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`CYCLE4 : tx_state[2:0] <= `CYCLE5;
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`CYCLE5 : tx_state[2:0] <= `CYCLE6;
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`CYCLE6 : tx_state[2:0] <= `CYCLE7;
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`CYCLE7 : tx_state[2:0] <= tx_burst_reg & ~tx_wait ? `CYCLE4 :
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`IDLE;
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//NOTE: Burst jumps into middle of state, except for on end of burst
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`CYCLE7 : tx_state[2:0] <= (tx_burst_reg & tx_burst) & ~tx_wait ? `CYCLE4 :
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`IDLE;
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endcase // case (tx_state)
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assign tx_new_frame = (tx_state[2:0]==`CYCLE1);
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reg [31:0] trans_counter;
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//A transaction counter for debugging, might be nice to put this in hardware, but then it should go in div4 domain
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`ifdef TARGET_SIM
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reg [31:0] trans_counter;
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always @ (posedge tx_lclk_io)
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if(!nreset)
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trans_counter[31:0]<='b0;
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@ -86,31 +86,8 @@ module etx_protocol (/*AUTOARG*/
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//Clear out the access while in wait state
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//the IO pipeline flushes out
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assign tx_access = tx_access_reg &
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// ~burst_negedge &
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~(tx_wr_wait | tx_rd_wait);
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//#################################
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//# Checking for transaction "done"
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//#################################
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//if burst, you get immediate "ack"
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//otherwise you get ack in one cycle
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reg done;
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wire tx_io_wait;
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always @ (posedge clk or negedge nreset)
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if(!nreset)
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done <= 1'b0;
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else
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done <= tx_access & ~done;
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assign tx_io_wait = tx_access & ~done & ~tx_burst;//tx_burst_reg
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assign adjust = tx_io_wait_reg & (tx_rd_wait | tx_wr_wait);
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//#############################
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//# Burst Detection
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//#############################
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packet2emesh p2m1 (
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.write_out (tx_write),
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.datamode_out (tx_datamode[1:0]),
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@ -119,7 +96,33 @@ module etx_protocol (/*AUTOARG*/
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.data_out (),
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.srcaddr_out (),
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.packet_in (tx_packet[PW-1:0]));//input
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//############################################################
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//# Checking for transaction "done"
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//#############################################################
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//if burst, you get immediate "ack"
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//otherwise you get ack in one cycle (since it takes 2 clocks for trans to exit IO)
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reg done;
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wire tx_io_wait;
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always @ (posedge clk or negedge nreset)
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if(!nreset)
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done <= 1'b0;
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else
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done <= tx_access & ~done & ~tx_burst;
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assign tx_io_wait = tx_access & ~done & ~tx_burst;//tx_burst_reg
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//Ugly hack. When there is an async wait coming in and we are in the middle of a transction
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//we sample in a new value to realign the pipeline since the current transaction already went
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//out to the IO.(must be a better way???)
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assign adjust = tx_io_wait_reg & (tx_rd_wait | tx_wr_wait);
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//#############################
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//# Burst Detection
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//#############################
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assign burst_addr_match = ((tx_dstaddr[31:0]+32'h8) == etx_dstaddr[31:0]);
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assign current_match = tx_access &
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@ -151,17 +154,16 @@ module etx_protocol (/*AUTOARG*/
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end
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assign tx_burst = tx_burst_reg &
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tx_burst_in &
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// tx_burst_in &
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~(tx_wr_wait | tx_rd_wait);
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assign burst_negedge = ~tx_burst_in &
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tx_burst_reg;
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//#############################
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//# Wait propagation circuit
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//#############################
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assign etx_wr_wait = (tx_wr_wait | tx_io_wait | burst_negedge) & ~adjust;
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assign etx_rd_wait = (tx_rd_wait | tx_io_wait | burst_negedge) & ~adjust;
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//#######################################
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//# Wait propagation circuit backwards
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//########################################
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assign etx_wr_wait = (tx_wr_wait | tx_io_wait ) & ~adjust;
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assign etx_rd_wait = (tx_rd_wait | tx_io_wait ) & ~adjust;
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endmodule // etx_protocol
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// Local Variables:
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