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Simplifying names to make it easier to specify generated clocks
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@ -91,10 +91,10 @@ module oh_clockdiv
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assign clk0_sel[0] = ~(clkdiv[7:0]==8'd0);
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oh_clockmux #(.N(2))
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iclkmux0 (.clkout(clkout0),
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.clk(clk),
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.en(clk0_sel[1:0]),
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.clkin({clk, clkout0_reg}));
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oh_clockmux0 (.clkout(clkout0),
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.clk(clk),
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.en(clk0_sel[1:0]),
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.clkin({clk, clkout0_reg}));
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//###########################################
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//# CLKOUT1
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@ -119,10 +119,10 @@ module oh_clockdiv
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assign clk1_sel[0] = |clkdiv[7:1]; // all others
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oh_clockmux #(.N(4))
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iclkmux1 (.clkout(clkout1),
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.clk(clk),
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.en( clk1_sel[3:0]),
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.clkin({1'b0, clk, clkout1_shift, clkout1_reg}));
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oh_clockmux1 (.clkout(clkout1),
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.clk(clk),
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.en( clk1_sel[3:0]),
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.clkin({1'b0, clk, clkout1_shift, clkout1_reg}));
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endmodule // oh_clockdiv
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@ -16,14 +16,14 @@ module oh_clockmux #(parameter ASIC = `CFG_ASIC, // use ASIC lib
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generate
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if(ASIC)
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begin : asic
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asic_clockmux #(.N(N)) imux (.clk(clk),
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.clkin(clkin[N-1:0]),
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.en(en[N-1:0]),
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.clkout(clkout));
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begin : g0
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asic_clockmux #(.N(N)) asic_clockmux (.clk(clk),
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.clkin(clkin[N-1:0]),
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.en(en[N-1:0]),
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.clkout(clkout));
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end
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else
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begin : generic
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begin : g0
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reg [N-1:0] en_sh;
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always @ (clk or en)
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if (!clk)
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