Fixing more synthesis warnings

src/common/hdl/oh_memory_ram.v

@@ -5,26 +5,24 @@
 //# License:  MIT  (see LICENSE file in OH! repository)                       # 
 //#############################################################################
 
-module oh_memory_ram  # (parameter DW    = 104,  //memory width
-			 parameter DEPTH = 32    //memory depth
+module oh_memory_ram  # (parameter DW    = 104,           //memory width
+			 parameter DEPTH = 32,            //memory depth
+			 parameter AW    = $clog2(DEPTH)  // address width  
 			 ) 
    (// read-port
-    input 	    rd_clk,// rd clock
-    input 	    rd_en, // memory access
-    input [AW-1:0]  rd_addr, // address
-    output [DW-1:0] rd_dout, // data output   
+    input 		rd_clk,// rd clock
+    input 		rd_en, // memory access
+    input [AW-1:0] 	rd_addr, // address
+    output reg [DW-1:0] rd_dout, // data output   
     // write-port
-    input 	    wr_clk,// wr clock
-    input 	    wr_en, // memory access
-    input [AW-1:0]  wr_addr, // address
-    input [DW-1:0]  wr_wem, // write enable vector    
-    input [DW-1:0]  wr_din // data input
+    input 		wr_clk,// wr clock
+    input 		wr_en, // memory access
+    input [AW-1:0] 	wr_addr, // address
+    input [DW-1:0] 	wr_wem, // write enable vector    
+    input [DW-1:0] 	wr_din // data input
     );
-
-   parameter AW      = $clog2(DEPTH);  // address bus width  
    
    reg [DW-1:0]        ram    [DEPTH-1:0];  
-   reg [DW-1:0]        rd_dout;
    integer 	       i;
       
    //registered read port

src/common/hdl/oh_pwr_gate.v

@@ -18,7 +18,7 @@ module oh_pwr_gate #(parameter ASIC = 0  // use ASIC lib
 `else
    generate
       if(ASIC)	
-	begin
+	begin : asic
 	   asic_pwr_header i_header (.npower(npower),
 				     .vdd(vdd),
 				     .vddg(vddg));

src/common/hdl/oh_pwr_isolate.v

@@ -6,7 +6,7 @@
 //#############################################################################
 
 module oh_pwr_isolate #(parameter DW   = 1, // width of data inputs
-			parameter ASIC = 0  // use ASIC lib
+			parameter ASIC = 1  // use ASIC lib
 			) 
    (
     input 	    vdd, // supply (set to 1 if valid)
@@ -23,14 +23,14 @@ module oh_pwr_isolate #(parameter DW   = 1, // width of data inputs
 `else
    generate
       if(ASIC)	
-	begin
+	begin : asic
 	   asic_iso i_iso [DW-1:0] (.vdd(vdd),
 				    .vss(vss),
 				    .in(in[DW-1:0]),
 				    .out(out[DW-1:0]));
 	end
       else
-	begin
+	begin : generic
 	   assign out[DW-1:0] = {(DW){niso}} & in[DW-1:0];
 	end
    endgenerate

src/edma/hdl/edma_ctrl.v

@@ -54,7 +54,10 @@ module edma_ctrl (/*AUTOARG*/
    wire [15:0] 	   fetch_addr;
    wire [AW-1:0]   srcaddr_out;
    wire [4:0] 	   reg_addr;
-   
+   wire 	   dma_error;
+   wire 	   incount_zero;
+   wire 	   outcount_zero;
+
    //###########################################
    //# STATE MACHINE                           
    //###########################################

src/edma/hdl/edma_regs.v

@@ -79,12 +79,16 @@ module edma_regs (/*AUTOARG*/
    reg [31:0] 	   status_reg;
 
    // wires
-   wire [4:0] 	   ctrlmode_out;
-   wire [AW-1:0]   data_out;
-   wire [1:0] 	   datamode_out;
-   wire [AW-1:0]   dstaddr_out;	
-   wire [AW-1:0]   srcaddr_out;
-   wire 	   write_out;
+   wire 	   reg_write;
+   wire 	   config_write;
+   wire 	   stride_write;
+   wire 	   count_write;
+   wire 	   srcaddr0_write;
+   wire 	   srcaddr1_write;
+   wire 	   dstaddr0_write;
+   wire 	   dstaddr1_write;
+   wire 	   status_write;
+   wire 	   irqmode;
 
    /*AUTOINPUT*/
    /*AUTOWIRE*/