diff --git a/common/dv/dv_ctrl.v b/common/dv/dv_ctrl.v
index fc075b4..5616818 100644
--- a/common/dv/dv_ctrl.v
+++ b/common/dv/dv_ctrl.v
@@ -10,7 +10,7 @@ module dv_ctrl(/*AUTOARG*/
    parameter CFG_CLK1_PHASE  = CFG_CLK1_PERIOD/2;
    parameter CFG_CLK2_PERIOD = 100;
    parameter CFG_CLK2_PHASE  = CFG_CLK2_PERIOD/2;
-   parameter CFG_TIMEOUT     = 5000;
+   parameter CFG_TIMEOUT     = 50000;
 
    output nreset;     // async active low reset
    output clk1;       // main clock
@@ -67,7 +67,7 @@ module dv_ctrl(/*AUTOARG*/
      begin	
 	#(1)
 	nreset   = 'b0;	
-	#(clk1_phase * 20)   //hold reset for 20 clk cycles
+	#(clk1_phase * 20 + 100)   //hold reset for 20 clk cycles
 	nreset   = 'b1;
      end
 
diff --git a/common/firmware/v2c.sh b/common/firmware/v2c.sh
new file mode 100755
index 0000000..de1dc83
--- /dev/null
+++ b/common/firmware/v2c.sh
@@ -0,0 +1,6 @@
+#!/bin/bash
+
+#translate verilog to a C header file (print to standard out)
+#$1 = verilog header file 
+ 
+
diff --git a/common/hdl/oh_memory_sp.v b/common/hdl/oh_memory_sp.v
index b350872..ddc4b8d 100644
--- a/common/hdl/oh_memory_sp.v
+++ b/common/hdl/oh_memory_sp.v
@@ -1,9 +1,9 @@
 module oh_memory_sp(/*AUTOARG*/
    // Outputs
-   dout, bist_dout,
+   dout,
    // Inputs
-   clk, en, we, wem, addr, din, vdd, vddm, sleep, shutdown,
-   cfg_repair, bist_en, bist_we, bist_wem, bist_addr, bist_din
+   clk, en, we, wem, addr, din, vdd, vddm, sleep, shutdown, repair,
+   bist_en, bist_we, bist_wem, bist_addr, bist_din
    );
 
    // parameters
@@ -27,7 +27,7 @@ module oh_memory_sp(/*AUTOARG*/
    input 	       vddm;       // array power rail     
    input 	       sleep;      // sleep (content retained)
    input 	       shutdown;   // shutdown (no retention)
-   input [RW-1:0]      cfg_repair; // "wildcard" repair vector   
+   input [RW-1:0]      repair;     // "wildcard" repair vector   
 
    // BIST interface (ASICs only)
    input 	       bist_en;   // bist enable
@@ -35,19 +35,18 @@ module oh_memory_sp(/*AUTOARG*/
    input [DW-1:0]      bist_wem;  // write enable vector
    input [AW-1:0]      bist_addr; // address
    input [DW-1:0]      bist_din;  // data input
-   output [DW-1:0]     bist_dout; // data output
    
 `ifdef CFG_ASIC
 
    //Actual IP hidden behind wrapper to protect the innocent
+
    sram_sp #(.DW(DW).
 	     .DEPTH(DEPTH),
 	     .PROJ(PROJ),
 	     .RW(RW))	     
-   sram_sp (/*AUTOINST*/
-	    // Outputs
+
+   sram_sp (// Outputs
 	    .dout			(dout[DW-1:0]),
-	    .bist_dout			(bist_dout[DW-1:0]),
 	    // Inputs
 	    .clk			(clk),
 	    .en				(en),