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Fixing broken empty signal
- Snuck in during the wip changes
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@ -32,7 +32,6 @@ module oh_fifo_cdc
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// wire declarations
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wire wr_en;
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wire rd_en;
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wire rd_empty;
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wire wr_almost_full;
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wire wr_full;
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wire wr_prog_full;
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@ -79,12 +78,12 @@ module oh_fifo_cdc
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.bist_dout (),
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.wr_count (),
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.rd_count (),
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.rd_empty (empty),
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/*AUTOINST*/
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// Outputs
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.wr_full (wr_full),
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.wr_almost_full (wr_almost_full),
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.wr_prog_full (wr_prog_full),
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.rd_empty (rd_empty),
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// Inputs
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.nreset (nreset),
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.wr_en (wr_en),
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