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Adding reset to synchronizer

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(cause there may not be a clock...)
This commit is contained in:
Andreas Olofsson 2015-04-27 16:03:57 -04:00
parent df53a2dc4f
commit 6b108f5e1f
4 changed files with 35 additions and 23 deletions
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6
elink/hdl/etx.v
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@ -173,7 +173,9 @@ module etx(/*AUTOARG*/
*/
//Write fifo (from slave)
wire txwr_access_gated = txwr_access & ~(txwr_packet[39:28]==ID);
wire txwr_access_gated = txwr_access & ~((txwr_packet[39:28]==ID) & (txwr_packet[27:24]==`EGROUP_TX)); //test feature, should never happen
fifo_async #(.DW(104), .AW(5)) txwr_fifo(.wr_en (txwr_access_gated),
.prog_full (txwr_wait),
.full (txwr_fifo_full),
@ -190,7 +192,7 @@ module etx(/*AUTOARG*/
.rd_en (txwr_fifo_read)); // Templated
//Read request fifo (from slave)
wire txrd_access_gated = txrd_access & ~(txrd_packet[39:28]==ID);
wire txrd_access_gated = txrd_access & ~((txrd_packet[39:28]==ID));
fifo_async #(.DW(104), .AW(5)) txrd_fifo(.wr_en (txrd_access_gated),
.prog_full (txrd_wait),
.full (txrd_fifo_full),

12
elink/hdl/etx_arbiter.v
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@ -82,15 +82,15 @@ module etx_arbiter (/*AUTOARG*/
//Current implementation can deadlock!! (move rd below rr)
// priority-based ready signals
assign wr_ready = ~txwr_fifo_empty & ~etx_wr_wait; //highest
assign rd_ready = ~txrd_fifo_empty & ~etx_rd_wait & ~wr_ready;
assign rr_ready = ~txrr_fifo_empty & ~etx_wr_wait & ~wr_ready & ~rd_ready;//lowest
assign wr_ready = ~txwr_fifo_empty & ~etx_wr_wait; //highest
assign rd_ready = ~txrd_fifo_empty & ~etx_rd_wait & ~wr_ready;
assign rr_ready = ~txrr_fifo_empty & ~etx_wr_wait & ~wr_ready & ~rd_ready;//lowest
// FIFO read enables (one hot)
// Hold until transaction has been accepted by IO
assign txrr_fifo_read = rr_ready & (~etx_access | etx_io_wait);
assign txrd_fifo_read = rd_ready & (~etx_access | etx_io_wait);
assign txwr_fifo_read = wr_ready & (~etx_access | etx_io_wait);
assign txrr_fifo_read = rr_ready & (~etx_access | etx_io_wait);
assign txrd_fifo_read = rd_ready & (~etx_access | etx_io_wait);
assign txwr_fifo_read = wr_ready & (~etx_access | etx_io_wait);
//Selecting control mode on slave transcations
assign txrd_ctrlmode[3:0] = ecfg_tx_ctrlmode_bp ? ecfg_tx_ctrlmode[3:0] :

24
elink/hdl/etx_protocol.v
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@ -112,8 +112,6 @@ module etx_protocol (/*AUTOARG*/
reg [127:0] tx_data_reg; //sample transaction on one clock cycle
reg rd_wait_sync;
reg wr_wait_sync;
reg etx_rd_wait;
reg etx_wr_wait;
wire etx_write;
wire [1:0] etx_datamode;
@ -201,13 +199,21 @@ module etx_protocol (/*AUTOARG*/
//# Wait signals (async)
//#############################
always @ (posedge tx_lclk_div4)
begin
rd_wait_sync <= tx_rd_wait;
etx_rd_wait <= rd_wait_sync;
wr_wait_sync <= tx_wr_wait;
etx_wr_wait <= wr_wait_sync;
end
synchronizer #(.DW(1)) rd_sync (// Outputs
.out (etx_rd_wait),
// Inputs
.in (tx_rd_wait),
.clk (tx_lclk_div4),
.reset (reset)
);
synchronizer #(.DW(1)) wr_sync (// Outputs
.out (etx_wr_wait),
// Inputs
.in (tx_wr_wait),
.clk (tx_lclk_div4),
.reset (reset)
);
//#############################
//# Pipeline stall

16
emmu/hdl/emmu.v
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@ -1,13 +1,17 @@
/*
###########################################################################
# Function: A address translator for the eMesh/eLink protocol
# Table writeable from mi_* configuration interface.
# 12 bit index used for table lookup (bits 31:20 of dstaddr)
# **EMMU**
#
# This block uses the upper 12 bits [31:20] of a memory address as an index
# to read an entry from a table.
#
# Assumes that output is always ready to receive. (no pushback)
# The table is written from the mi_* configuration interface.
#
# The table can be configured as 12 bits wide or 44 bits wide.
#
# 32bit address output = {table_data[11:0],dstaddr[19:0]}
# 64bit address output = {table_data[43:0],dstaddr[19:0]}
#
# 32bit address output = {table_data[11:0],dstaddr[19:0]}
# 64bit address output = {table_data[43:0],dstaddr[19:0]}
#
############################################################################
*/