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Improving sys_reset timing

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- removing pass through path
- registering sys_reset input
This commit is contained in:
Andreas Olofsson 2015-10-08 10:33:38 -04:00
parent 86e8579e48
commit 6d2b3d63fe
1 changed files with 18 additions and 10 deletions
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28
elink/hdl/etx_clocks.v
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@ -2,7 +2,7 @@
module etx_clocks (/*AUTOARG*/ module etx_clocks (/*AUTOARG*/
// Outputs // Outputs
tx_lclk, tx_lclk90, tx_lclk_div4, cclk_p, cclk_n, etx_reset, tx_lclk, tx_lclk90, tx_lclk_div4, cclk_p, cclk_n, etx_reset,
etx_io_reset, chip_resetb, etx_io_reset, chip_resetb, tx_active,
// Inputs // Inputs
sys_reset, soft_reset, sys_clk sys_reset, soft_reset, sys_clk
); );
@ -46,7 +46,8 @@ module etx_clocks (/*AUTOARG*/
output etx_reset; // reset for tx core logic output etx_reset; // reset for tx core logic
output etx_io_reset; // io reset (synced to high speed clock) output etx_io_reset; // io reset (synced to high speed clock)
output chip_resetb; // reset fpr Epiphany chip output chip_resetb; // reset fpr Epiphany chip
output tx_active; // enable for rx path (ensures active clock)
//############ //############
//# WIRES //# WIRES
//############ //############
@ -104,9 +105,15 @@ module etx_clocks (/*AUTOARG*/
`define HOLD_IT 3'b100 //??? `define HOLD_IT 3'b100 //???
`define ACTIVE 3'b101 `define ACTIVE 3'b101
//Reset sequence state machine
always @ (posedge sys_clk or posedge sys_reset) //pipeline reset to improve timing
if(sys_reset) reg por_reset;
always @ (posedge sys_clk)
por_reset <= sys_reset;
//Reset sequence state machine
always @ (posedge sys_clk or posedge por_reset)
if(por_reset)
reset_state[2:0] <= `RESET_ALL; reset_state[2:0] <= `RESET_ALL;
else if(heartbeat) else if(heartbeat)
case(reset_state[2:0]) case(reset_state[2:0])
@ -132,8 +139,7 @@ module etx_clocks (/*AUTOARG*/
//reset mmcm (async) //reset mmcm (async)
assign mmcm_reset = (reset_state[2:0]==`RESET_ALL) | assign mmcm_reset = (reset_state[2:0]==`RESET_ALL) |
(reset_state[2:0]==`STOP_CCLK) | (reset_state[2:0]==`STOP_CCLK) |
(reset_state[2:0]==`DEASSERT_RESET) | (reset_state[2:0]==`DEASSERT_RESET)
sys_reset
; ;
//reset chip (active low) //reset chip (active low)
@ -142,8 +148,10 @@ module etx_clocks (/*AUTOARG*/
(reset_state[2:0]==`ACTIVE); (reset_state[2:0]==`ACTIVE);
//reset the elink //reset the elink
wire tx_reset = sys_reset | wire tx_reset = (reset_state[2:0] != `ACTIVE);
(reset_state[2:0] != `ACTIVE);
assign tx_active = (reset_state[2:0] == `ACTIVE);
//############################# //#############################
//#RESET SYNC //#RESET SYNC
@ -263,7 +271,7 @@ module etx_clocks (/*AUTOARG*/
.CE (1'b1), .CE (1'b1),
.D1 (1'b1), .D1 (1'b1),
.D2 (1'b0), .D2 (1'b0),
.R (sys_reset), .R (1'b0),
.S (1'b0)); .S (1'b0));
//CCLK differential buffer //CCLK differential buffer