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Hold hack..

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-This needs to be resolved! Currently there is a simulation problem with the PLL and IDDR circuit, likely due to the clock divider. Amazingly enough the circuit works in sim and FPGA, but there was some redundant logic hiding this.
-Need to take a closer look at this to get the non-blocking/blocking right in PLL and CLKDIV
This commit is contained in:
Andreas Olofsson 2016-01-19 16:01:15 -05:00
parent b26255dfb5
commit 6e93d0399a
2 changed files with 14 additions and 12 deletions
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10
xilibs/hdl/IDDR.v
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@ -13,6 +13,8 @@ module IDDR (/*AUTOARG*/
parameter [0:0] IS_D_INVERTED = 1'b0; parameter [0:0] IS_D_INVERTED = 1'b0;
parameter SRTYPE = "SYNC"; parameter SRTYPE = "SYNC";
localparam HOLDHACK = 0.1;
output Q1; // IDDR registered output (first) output Q1; // IDDR registered output (first)
output Q2; // IDDR registered output (second) output Q2; // IDDR registered output (second)
input C; // clock input C; // clock
@ -32,19 +34,19 @@ module IDDR (/*AUTOARG*/
always @ (posedge C) always @ (posedge C)
if(CE) if(CE)
Q1_pos <= D; Q1_pos <= #(HOLDHACK) D;
always @ (posedge C) always @ (posedge C)
if(CE) if(CE)
Q1_reg <= Q1_pos; Q1_reg <= #(HOLDHACK) Q1_pos;
always @ (negedge C) always @ (negedge C)
if(CE) if(CE)
Q2_neg <= D; Q2_neg <= #(HOLDHACK) D;
always @ (posedge C) always @ (posedge C)
if(CE) if(CE)
Q2_pos <= Q2_neg; Q2_pos <= #(HOLDHACK) Q2_neg;
//Select behavior based on parameters //Select behavior based on parameters
assign Q1 = (DDR_CLK_EDGE_REG == "SAME_EDGE_PIPELINED") ? Q1_reg : assign Q1 = (DDR_CLK_EDGE_REG == "SAME_EDGE_PIPELINED") ? Q1_reg :

14
xilibs/hdl/PLLE2_ADV.v
View File

@ -152,7 +152,7 @@ module PLLE2_ADV #(
`else `else
always @ (posedge (CLKIN1 & vco_clk) or negedge (CLKIN1&~vco_clk)) always @ (posedge (CLKIN1 & vco_clk) or negedge (CLKIN1&~vco_clk))
begin begin
CLKOUT_DIV_LOCK[5:0] <= CLKOUT_DIV[5:0]; CLKOUT_DIV_LOCK[5:0] = CLKOUT_DIV[5:0];
end end
`endif `endif
@ -168,12 +168,12 @@ module PLLE2_ADV #(
always @ (CLKOUT_DIV_LOCK) always @ (CLKOUT_DIV_LOCK)
begin begin
CLKOUT0 <= #(CLK0_DELAY) ~reset & CLKOUT_DIV_LOCK[0]; CLKOUT0 = #(CLK0_DELAY) ~reset & CLKOUT_DIV_LOCK[0];
CLKOUT1 <= #(CLK1_DELAY) ~reset & CLKOUT_DIV_LOCK[1]; CLKOUT1 = #(CLK1_DELAY) ~reset & CLKOUT_DIV_LOCK[1];
CLKOUT2 <= #(CLK2_DELAY) ~reset & CLKOUT_DIV_LOCK[2]; CLKOUT2 = #(CLK2_DELAY) ~reset & CLKOUT_DIV_LOCK[2];
CLKOUT3 <= #(CLK3_DELAY) ~reset & CLKOUT_DIV_LOCK[3]; CLKOUT3 = #(CLK3_DELAY) ~reset & CLKOUT_DIV_LOCK[3];
CLKOUT4 <= #(CLK4_DELAY) ~reset & CLKOUT_DIV_LOCK[4]; CLKOUT4 = #(CLK4_DELAY) ~reset & CLKOUT_DIV_LOCK[4];
CLKOUT5 <= #(CLK5_DELAY) ~reset & CLKOUT_DIV_LOCK[5]; CLKOUT5 = #(CLK5_DELAY) ~reset & CLKOUT_DIV_LOCK[5];
end end
//############## //##############