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Adding links to all common modules

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Andreas Olofsson 2016-03-22 09:17:01 -04:00
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src/common/README.md
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Common Module Library
===============================================
| Name | Done | Function |
|-----------------|------|-------------------------------------|
| oh_rsync | Y | Reset synchronzation circuit |
| oh_dsync | Y | Data synchronizizer |
| oh_mux{N} | Y | Various one-hot muxes |
| oh_edgealign | Y | Aligns slow pulse to fast clock |
| oh_pulse2pulse | Y | Converts fast pulse to slow pulse |
| oh_stretcher | Y | Stetches a pulse |
| oh_clockdiv | N | Clock divider |
| oh_arbiter | N | Configurable arbiter |
| oh_fifo_sync | Y | FIFO with same rd/wr clocks |
| oh_fifo_async | Y | FIFO with seaprate rd/wr clocks |
| oh_fifo_cdc | Y | Clock domain crossing FIFO |
| oh_memory_sp | Y | Single ported memory |
| oh_memory_dp | Y | Dual ported memory |
| oh_standby | Y | Low power standby circuit |
| oh_clockgate | Y | Low power clock gating circuit |
| oh_datagate | Y | Low power data gating circuit |
| oh_lat0 | Y | Latch (active low) |
| oh_lat1 | Y | Latch (active high) |
| oh_add | Y | Binary adder |
| oh_csa32 | Y | Full adder |
| oh_csa42 | Y | CSA4:2 Compressor |
| oh_abs | N | Absolute value circuit |
| oh_shifter | N | Binary shifter |
| oh_bin2gray | N | Binary to gray converter |
| oh_gray2bin | N | Gray to binary converter |
| oh_counter | N | Multi-type counter |
| oh_crc | N | CRC generator |
| oh_par2ser | N | Parallel to serial converter |
| oh_ser2par | N | Serial to parallel converter |
| Name |Done| Function |
|--------------------------------------------|:--:|--------------------------------|
| [oh_8b10b_decode](hdl/oh_8b10b_decode.v) | N | 8b10b decoder |
| [oh_8b10b_encode](hdl/oh_8b10b_encode.v) | N | 8b10b encoder |
| [oh_abs](hdl/oh_abs.v) | Y | Absolute value calculator |
| [oh_add](hdl/oh_add.v) | Y | Binary adder |
| [oh_arbiter](hdl/oh_arbiter.v) | Y | Configurable arbiter |
| [oh_bin2gray](hdl/oh_bin2gray.v) | Y | Binary to gray converter |
| [oh_bitreverse](hdl/oh_bitreverse.v) | Y | Bitreverse circuit |
| [oh_clockdiv](hdl/oh_clockdiv.v) | Y | Combinatorial clock divider |
| [oh_clockgate](hdl/oh_clockgate.v) | Y | Clock gater |
| [oh_counter](hdl/oh_counter.v) | Y | Binary counter |
| [oh_crc](hdl/oh_crc.v) | Y | CRC encoder |
| [oh_csa32](hdl/oh_csa32.v) | Y | Carry save adder 3:2 |
| [oh_csa42](hdl/oh_csa42.v) | Y | Carry save adder 4:2 |
| [oh_csa62](hdl/oh_csa62.v) | Y | Carry save adder 6:2 |
| [oh_csa92](hdl/oh_csa92.v) | Y | Carry save adder 9:2 |
| [oh_datagate](hdl/oh_datagate.v) | Y | Data gater |
| [oh_debouncer](hdl/oh_debouncer.v) | Y | Button debouncer |
| [oh_dsync](hdl/oh_dsync.v) | Y | Data synchronizizer |
| [oh_edge2pulse](hdl/oh_edge2pulse.v) | Y | Converts edge to pulse |
| [oh_edgealign](hdl/oh_edgealign.v) | Y | Fast/slow clock alignment |
| [oh_edgedetect](hdl/oh_edgedetect.v) | Y | Configurable edge detector |
| [oh_fall2pulse](hdl/oh_fall2pulse.v) | Y | Converts falling edge to pulse |
| [oh_fifo_async](hdl/oh_fifo_async.v) | Y | Asynchonous FIFO (dual clock) |
| [oh_fifo_cdc](hdl/oh_fifo_cdc.v) | Y | Clock domain crossing FIFO |
| [oh_fifo_generic](hdl/oh_fifo_generic.v) | Y | Generic synchronous FIFO |
| [oh_fifo_sync](hdl/oh_fifo_sync.v) | Y | Synchronous FIFO |
| [oh_gray2bin](hdl/oh_gray2bin.v) | Y | Gray to binary converter |
| [oh_iddr](hdl/oh_iddr.v) | Y | Dual data rate input buffer |
| [oh_lat0](hdl/oh_lat0.v) | Y | Latch on low clock |
| [oh_lat1](hdl/oh_lat1.v) | Y | latch on high clock |
| [oh_memory_dp](hdl/oh_memory_dp.v) | Y | Dual ported memory |
| [oh_memory_sp](hdl/oh_memory_sp.v) | Y | Single ported memory |
| [oh_mux12](hdl/oh_mux12.v) | Y | Twelve port mux |
| [oh_mux2](hdl/oh_mux2.v) | Y | Two port mux |
| [oh_mux3](hdl/oh_mux3.v) | Y | Three port mux |
| [oh_mux4](hdl/oh_mux4.v) | Y | Four port mux |
| [oh_mux5](hdl/oh_mux5.v) | Y | Five port mux |
| [oh_mux6](hdl/oh_mux6.v) | Y | Six port mux |
| [oh_mux7](hdl/oh_mux7.v) | Y | Seven port mux |
| [oh_mux8](hdl/oh_mux8.v) | Y | Eight port mux |
| [oh_mux9](hdl/oh_mux9.v) | Y | Ten port mux |
| [oh_mux](hdl/oh_mux.v) | Y | Generic n-port mux |
| [oh_oddr](hdl/oh_oddr.v) | Y | Dual data rate output buffer |
| [oh_par2ser](hdl/oh_par2ser.v) | Y | Parallel to serial converter |
| [oh_parity](hdl/oh_parity.v) | Y | Parity calculator |
| [oh_pulse2pulse](hdl/oh_pulse2pulse.v) | Y | Pulse to pulse CDC circuit |
| [oh_rise2pulse](hdl/oh_rise2pulse.v) | Y | Rising edge to pulse converter |
| [oh_rsync](hdl/oh_rsync.v) | Y | Reset synchronzation circuit |
| [oh_ser2par](hdl/oh_ser2par.v) | Y | Serial to parallel converter |
| [oh_shifter](hdl/oh_shifter.v) | Y | Bit shifter |
| [oh_standby](hdl/oh_standby.v) | Y | Standby circuit |
| [oh_stretcher](hdl/oh_stretcher.v) | Y | Pulse stretcher |