Reorg! Why?

- The top level directory was not scaling, too imposing
- Friendlier to download a repo and see a finite number of top level dirs
- We are just getting started...

CODING-METHODOLOGY.md

@@ -1,55 +0,0 @@
-CODING METHODOLOGY
-========================================================
-
-## STANDARD
-* Verilog 2005
-
-## STYLE
-* Max 80 chars per line
-* One input/output statement per line
-* Only single line // comments, no /*..*/
-* Use vector sizes in every statement, ie "assign a[7:0] = myvec[7:0];"
-* Use parameters for reusability and readability
-* Use many short statements in place of one big one
-* Define wires/regs at beginning of file
-* Align input names/comments in column like fashion
-* Avoid redundant begin..end statements
-* Capitalize macros and constants
-* Use lower case for all signal names
-* User upper case for all parameters and constants
-* Use y down to x vectors
-* Use a naming methodology and document it
-* Comment every module port
-* Do not hard code numerical values in body of code
-* Keep parameter names short
-* Use common names: nreset, clk, din, dout, en, rd, wr, addr, etc
-* Make names as short as possible, but not shorter
-* Use _ in constants over 4 bits (eg: 8'h1100_1100)
-
-## METHODLOGY
-* Use `include files for constants
-* Use `ifndef _CONSTANTS_V to include file only once
-* No timescales in design files (only in testbench)
-* No delay statements in design
-* No logic statements in top level design structures
-* One module per file
-* Prefer parameters in place of global defines
-* Do not use casex
-* Use active low reset
-* Avoid redundant resets
-* Avoid heavily nested if, else statements
-* Don't use defparams, place #(.DW(DW)) in module instantation
-* Always use connection by name (not by order) in module instantiatoin
-* Parametrize as much as possible but not more
-* Place a useful comment every 5-20 lines
-* If you are going to use async reset, use oh_rsync.v
-* Use for loops to reduce bloat and to improve readability
-* If you have to mix clock edges, isolate to discrete modules
-* Use nonblocking (<=) in all sequential statements
-* Use default statements in all case statements
-* Don't use proprietary EDA tool pragmas (use parameters)
-* Only use synthesizable constructs
-* Use $signed() for arithmetic operations on signed types
-* Allowed keywords: assign, always, input, output, wire, reg, module, endmodule, if/else, case, casez, ~,|,&,^,==, >>, <<, >, <,?,posedge, negedge, generate, for(...), begin, end, $signed,
-
-

CONTRIBUTING.md

@@ -1,102 +0,0 @@
-# Contributing to "OH"
-
-If you are interested in contributing to OH!, here are some instructions to get you started. Thank you!
-
-### Coding Guidelines
-* Language: Verilog
-* Style: A coding manual to be published soon (stay tuned)
-
-### Contribution advice
-* Keep changes small (especially if you are a new contributor)
-* You are responsible for not breaking something with your PR
-* Include examples/test code for pull request
-
-### Contribution Conventions
-* If it's a bug fix branch, name it XXXX-something where XXXX is the number of
-the issue.
-* If it's a feature branch, create an enhancement issue to announce your
-  intentions, and name it XXXX-something where XXXX is the number of the issue.
-* Pull requests descriptions should be as clear as possible and include a
-reference to all the issues that they address. 
-* Commit messages must start with a capitalized and short summary (max. 50
-chars) written in the imperative, followed by an optional, more detailed
-explanatory text which is separated from the summary by an empty line.
-* Code review comments may be added to your pull request. Discuss, then make 
-the suggested modifications and push additional commits to your feature branch. Be sure to post a comment after pushing. The new commits will show up in the 
-pull request automatically, but the reviewers will not be notified unless you
-comment.
-* Pull requests must be cleanly rebased ontop of master without multiple branches mixed into the PR.
-* Before the pull request is merged, make sure that you squash your commits into
-logical units of work using `git rebase -i` and `git push -f`. After every
-commit the test suite should be passing. Include documentation changes in the
-same commit so that a revert would remove all traces of the feature or fix.
-
-
-### How to submit a pull request?
-
-1. Modify the code
-2. Run and pass the regression suite
-3. Submit a pull request:
- 
-### How to file a bug report?
-For standard issues like bugs and documentation errors please fill out an [issue ticket](https://github.com/parallella/oh/issues)
-
-### How to submit a feature proposals?
-
-0. Check the [Parallella forum](https://forums.parallella.org/) and [Issue Manager](https://github.com/parallella/oh/issues) for work in progress
-1. Describe the problem the proposal solves
-2. Provide a compelling use case
-3. Post and discuss your proposal on the [Parallella forum](https://forums.parallella.org/)
-4. Submit a pull request that modifies the documentation and adding new documentation as necessary
-
-### Signoff Requirement
-
-All major code contribution requires a sign-off. The sign-off is a simple line at the end of the explanation for the patch, which certifies that you wrote it or otherwise have the right to pass it on as an open-source patch.  The rules are pretty simple: if you can certify the below (from
-[developercertificate.org](http://developercertificate.org/)):
-
-```
-Developer Certificate of Origin
-Version 1.1
-
-Copyright (C) 2004, 2006 The Linux Foundation and its contributors.
-660 York Street, Suite 102,
-San Francisco, CA 94110 USA
-
-Everyone is permitted to copy and distribute verbatim copies of this
-license document, but changing it is not allowed.
-
-Developer's Certificate of Origin 1.1
-
-By making a contribution to this project, I certify that:
-
-(a) The contribution was created in whole or in part by me and I
-    have the right to submit it under the open source license
-    indicated in the file; or
-
-(b) The contribution is based upon previous work that, to the best
-    of my knowledge, is covered under an appropriate open source
-    license and I have the right under that license to submit that
-    work with modifications, whether created in whole or in part
-    by me, under the same open source license (unless I am
-    permitted to submit under a different license), as indicated
-    in the file; or
-
-(c) The contribution was provided directly to me by some other
-    person who certified (a), (b) or (c) and I have not modified
-    it.
-
-(d) I understand and agree that this project and the contribution
-    are public and that a record of the contribution (including all
-    personal information I submit with it, including my sign-off) is
-    maintained indefinitely and may be redistributed consistent with
-    this project or the open source license(s) involved.
-```
-
-Then you just add a line to every git commit message:
-
-    Signed-off-by: Joe Smith <joe.smith@email.com>
-
-Using your real name (sorry, no pseudonyms or anonymous contributions.)
-
-If you set your `user.name` and `user.email` git configs, you can sign your
-commit automatically with `git commit -s`.

README.md

@@ -1,7 +1,7 @@
 =======
 # OH! Open Hardware
 
-![alt tag](common/docs/lego.jpg)
+![alt tag](docs/lego.jpg)
 
 ## Content
 
@@ -28,25 +28,24 @@
 
 ## Modules
 
-| FOLDER                             | STATUS| DESCRIPTION                    |
-|------------------------------------|-------|--------------------------------|
-|[accelerator](accelerator/README.md)| FPGA  | Accelerator tutorial           |
-|[axi](axi/README.md)                | FPGA  | AXI master and slave interfaces|
-|[chip](chip/README.md)              | SI    | Chip design reference flow     |
-|[common](common/README.md)          | SI    | Library of basic components    |
-|[elink](elink/README.md)            | SI    | Point to point LVDS link       |
-|[emailbox](emailbox/README.md)      | FPGA  | Mailbox with interrupt output  |
-|[emesh](emesh/README.md)            | SI    | Emesh interface circuits       |
-|[emmu](emmu/README.md)              | FPGA  | Memory translation unit        |
-|[etrace](etrace/README.md)          | HH    | Logic Analyzer                 |
-|[gpio](gpio/README.md)              | HH    | General Purpose IO             |
-|[mio](mio/README.md)                | HH    | Lightweight parallel link      |
-|[pic](pic/README.md)                | SI    | Interrupt controller           |
-|[parallella](parallella/README.md)  | FPGA  | Parallella FPGA logic          |
-|[risc-v](risc-v/README.md)          | HH    | RISC-V implementation          |
-|[spi](spi/README.md)                | HH    | SPI master/slave               |
-|[verilog](verilog/README.md)        | HH    | Verilog referenca material     |
-|[xilibs](xilibs/README.md)          | FPGA  | Xilinx simulation models       |
+| FOLDER                                 | STATUS| DESCRIPTION                    |
+|----------------------------------------|-------|--------------------------------|
+|[accelerator](src/accelerator/README.md)| FPGA  | Accelerator tutorial           |
+|[axi](src/axi/README.md)                | FPGA  | AXI master and slave interfaces|
+|[chip](src/chip/README.md)              | SI    | Chip design reference flow     |
+|[common](src/common/README.md)          | SI    | Library of basic components    |
+|[elink](src/elink/README.md)            | SI    | Point to point LVDS link       |
+|[emailbox](src/emailbox/README.md)      | FPGA  | Mailbox with interrupt output  |
+|[emesh](src/emesh/README.md)            | SI    | Emesh interface circuits       |
+|[emmu](src/emmu/README.md)              | FPGA  | Memory translation unit        |
+|[etrace](src/etrace/README.md)          | HH    | Logic Analyzer                 |
+|[gpio](src/gpio/README.md)              | HH    | General Purpose IO             |
+|[mio](src/mio/README.md)                | HH    | Lightweight parallel link      |
+|[pic](src/pic/README.md)                | SI    | Interrupt controller           |
+|[parallella](src/parallella/README.md)  | FPGA  | Parallella FPGA logic          |
+|[risc-v](src/risc-v/README.md)          | HH    | RISC-V implementation          |
+|[spi](src/spi/README.md)                | HH    | SPI master/slave               |
+|[xilibs](src/xilibs/README.md)          | FPGA  | Xilinx simulation models       |
 
 **NOTES:**
 * "SI"= Silicon validated
@@ -58,9 +57,9 @@
 ## How to simulate
 
 ```sh
-./build.sh gpio/dv/dut_gpio.v         # compile gpio testbench (example)
-./sim.sh gpio/dv/tests/test_basic.emf # run a simulation with "test_regs.emf"
-./view.sh                             # open the waveform with gtkwave
+./scripts/build.sh gpio/dv/dut_gpio.v         # compile gpio testbench (example)
+./scripts/sim.sh gpio/dv/tests/test_basic.emf # run a simulation with "test_regs.emf"
+./scripts/view.sh                             # open the waveform with gtkwave
 ```
 
 **Short-cut:**
@@ -193,9 +192,9 @@ TBD
 
 ## Recommended Reading
 
-* [Verilog Reference](verilog/verilog_reference.md)
-* [Glossary](chip/docs/glossary.md)
-* [Chip constants](chip/docs/constants.md)
+* [Verilog Reference](docs/verilog_reference.md)
+* [Glossary](docs/chip_glossary.md)
+* [Chip constants](docs/chip_constants.md)
 * [Verilator Simulator](http://www.veripool.org/wiki/verilator)
 * [Emacs Verilog Mode](http://www.veripool.org/wiki/verilog-mode)
 * [Icarus Simulator](http://iverilog.icarus.com)

chip/docs/constants.md

@@ -1,61 +0,0 @@
-USEFUL CONSTANTS
-========================
-
-A list of some basic equations and constants I have found useful in my life as a chip and board designer. 
-
-## Basic Laws
-
-| Rule                               | Value                                 |
-|------------------------------------|---------------------------------------|
-| Speed of light                     | c = 299,792,458 m/s (~3.00x10^8 m/s)  |
-| Vacuum permitivity                 | eps0 = 8.854187817 x 10-12 F/m        | 
-| Vacuum permeability                | u0   = 4pi x 10-7 H / m or (V*s/A*m)  |
-| Time of Flight (air)               | 3.35 ps/mm                            |
-| Capacitance (parallel plate)       | C = k * eps0 * Area / d               |
-| Inductance (wire/ground plan)      | L = (u/2pi) * ln ( 4 * h / d)         |
-| Capacitor current                  | I = C * dV / dt                       |
-| Inductor voltage                   | V = L * dI / dt                       |
-| Resistor voltage                   | V = I * R                             |
-| Charge on capacitor                | Q = C * V                             |
-| Power                              | P = I * V                             |
-| Dynaminc power for capacitive load | P = Freq * Cap * VDD^2                |
-| Energy                             | E = P * t                             |
-
-## Board Design
-
-| Rule                               | Value                                 |
-|------------------------------------|---------------------------------------|
-| Lumped system rule of thumb (mm)   | length < 1/6*Rise_time/time_of_flight |
-| Time of Flight (FR4-inner layer)   | 7.09 ps/mm                            |
-
-## Chip Design
-
-| Rule                              | Value                                 |
-|-----------------------------------|---------------------------------------|
-| De Morgan's Law                   |~(A AND B)=~A OR ~B,~(A OR B)=~A AND ~B|
-| RC delay                          | (0.35) * res/um * cap/um * L(um)^2    |
-| Relative permitivity (SiO2)       | 3.9                                   |
-| Relative permitivity (Si)         | 11.68                                 |
-| Line capacitance/mm (max density) |           (highly variable!)          |
-| Line resistance/mm (fat layer)    |           (copper, highly variable!)  |
-
-## Interconnects
-
-| Rule                                | Value                                 |
-|-------------------------------------|---------------------------------------|
-| Chip wire pitch                     | ~0.1um                                |
-| 2.5D wire pitch                     | 4um                                   |
-| Wirebond pitch                      | 30um                                  |
-| 2.5D Bump pitch                     | 45um                                  |
-| Flip-chip pitch                     | 170um                                 |
-| BGA pitch (advanced)                | 400um                                 |
-| BGA pitch (standard)                | 1000um                                |
-| Hobby "solderable" connector        | 2540um                                |
-| Ethernet connector                  | ~10,000um                             |
-
-
-
-
-
-
-