Adding basic random HW random number generator

-work in progress...

src/stdlib/dv/tb_oh_random.v

@@ -0,0 +1,43 @@
+module testbench();
+
+   localparam N = 32;
+
+   /*AUTOINPUT*/
+   /*AUTOWIRE*/
+   // Beginning of automatic wires (for undeclared instantiated-module outputs)
+   wire			clk1;			// From oh_simctrl of oh_simctrl.v
+   wire			clk2;			// From oh_simctrl of oh_simctrl.v
+   wire			nreset;			// From oh_simctrl of oh_simctrl.v
+   wire [N-1:0]		out;			// From oh_random of oh_random.v
+   wire			start;			// From oh_simctrl of oh_simctrl.v
+   wire			vdd;			// From oh_simctrl of oh_simctrl.v
+   wire			vss;			// From oh_simctrl of oh_simctrl.v
+   // End of automatics
+
+   oh_random #(.N(N))
+   oh_random(.en		(1'b1),
+	     .clk		(clk1),
+	     /*AUTOINST*/
+	     // Outputs
+	     .out			(out[N-1:0]),
+	     // Inputs
+	     .nreset			(nreset));
+
+   oh_simctrl oh_simctrl(//TODO: implement
+			.stim_done	(1'b0),
+			.test_done	(1'b0),
+			.test_diff	(1'b0),
+			.dut_active     (1'b1),
+			/*AUTOINST*/
+			 // Outputs
+			 .nreset		(nreset),
+			 .clk1			(clk1),
+			 .clk2			(clk2),
+			 .start			(start),
+			 .vdd			(vdd),
+			 .vss			(vss));
+
+endmodule // tb
+// Local Variables:
+// verilog-library-directories:("." "../hdl")
+// End:

src/stdlib/hdl/oh_random.v

@@ -0,0 +1,48 @@
+//#############################################################################
+//# Function: Random number generator
+//#############################################################################
+//# Author:   Andreas Olofsson                                                #
+//# License:  MIT (see LICENSE file in OH! repository)                        #
+//#############################################################################
+
+module oh_random
+  #(parameter N    = 32 //width of counter (max value)
+    )
+   (
+    input 	   clk,
+    input 	   nreset, //async reset
+    input 	   en, //enable counter
+    output [N-1:0] out  //random output pulse
+    );
+
+   wire [N-1:0]   taps_sel;
+   reg [N-1:0] 	  lfsr_reg;
+   wire [N-1:0]   lfsr_in;
+
+   // LFSR tap selector (TODO: complete table)
+   generate
+      case(N)
+	32: assign taps_sel[31:0] = 32'h80000057<<1;
+      endcase // case (N)
+
+   endgenerate
+
+   // counter
+   always @(posedge clk or negedge nreset)
+     if(~nreset)
+       lfsr_reg[N-1:0] <= {(N/2){2'b01}};
+     else if(en)
+       lfsr_reg[N-1:0] <= lfsr_in[N-1:0];
+
+   assign feedback         = lfsr_reg[N-1]; //feedback from MSB
+   assign lfsr_in[0]       = feedback; //unconditional feedback for [0]
+
+   genvar 	  i;
+   for(i=1;i<N;i=i+1)
+     assign lfsr_in[i] = taps_sel[i] ? (lfsr_reg[i-1] ^ feedback) :
+		         lfsr_reg[i-1];
+
+   assign out[N-1:0] = lfsr_reg[N-1:0];
+
+
+endmodule // oh_random