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MILESTONE: register read/write working!

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-Bullet proof clock domain crossings!
This commit is contained in:
Andreas Olofsson 2015-05-04 10:49:17 -04:00
parent bb8f5f861b
commit 72aff72558
10 changed files with 95 additions and 104 deletions
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28
elink/README.md
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@ -188,7 +188,7 @@ elink
The full 32 bit physical address of an elink register is the address seen below
added to the 12 bit elink ID that maps to address bits 31:20. As an example,
if the elink ID is 0x810, then writing to the E_RESET register would be done to
address 0x810F0200.
address 0x810F0200. Redback is done through the txrd channel wit the source address sub field set to 810Dxxxx;
REGISTER | AC | ADDRESS | DESCRIPTION
---------------|----|---------|------------------
@ -208,22 +208,15 @@ ETX_DMADSTADDR | RW | 0xF0510 | RX DMA slave buffer (lo)
ETX_DMAAUTO0 | RW | 0xF0514 | RX DMA slave buffer (hi)
ETX_DMAAUTO1 | RW | 0xF0518 | RX DMA slave buffer (hi)
ETX_DMASTATUS | RW | 0xF051c | RX DMA status
ETX_DMADESCR0 | RW | 0xF0580 | RX DMA {reserved,config}
ETX_DMADESCR1 | RW | 0xF0584 | TX DMA {dst_stride[15:0],src_stride[15:0]}
ETX_DMADESCR2 | RW | 0xF0588 | TX DMA {reserved,count[15:0]}
ETX_DMADESCR3 | RW | 0xF058c | TX reserved
ETX_DMADESCR4 | RW | 0xF0590 | TX DMA srcaddr[31:0]
ETX_DMADESCR5 | RW | 0xF0594 | TX DMA dstaddr[31:0]
***************|****|*********|********************
ETX_MMU | -W | 0xE0000 | TX MMU table
***************|****|*********|********************
ERX_CFG | RW | 0xF0300 | RX configuration
ERX_STATUS | R- | 0xF0304 | RX status register
ERX_GPIO | R | 0xF0308 | RX data in GPIO mode
ERX_RR | RW | 0xF030c | RX read response address
ERX_OFFSET | RW | 0xF0310 | RX memory offset in remap mode
ERX_MAILBOXLO | RW | 0xF0314 | RX mailbox (lower 32 bit)
ERX_MAILBOXHI | RW | 0xF0318 | RX mailbox (upper 32 bits)
ERX_OFFSET | RW | 0xF030C | RX memory offset in remap mode
ERX_MAILBOXLO | RW | 0xF0310 | RX mailbox (lower 32 bit)
ERX_MAILBOXHI | RW | 0xF0314 | RX mailbox (upper 32 bits)
ERX_DMACFG | RW | 0xF0520 | TX DMA configuration
ERX_DMACOUNT | RW | 0xF0524 | TX DMA count
ERX_DMASTRIDE | RW | 0xF0528 | TX DMA stride
@ -232,11 +225,6 @@ ERX_DMADSTADDR | RW | 0xF0530 | TX DMA destination address
ERX_DMAAUTO0 | RW | 0xF0534 | TX DMA slave buffer (lo)
ERX_DMAAUTO1 | RW | 0xF0538 | TX DMA slERXave buffer (hi)
ERX_DMASTATUS | RW | 0xF053c | TX DMA status
ERX_DMADESCR0 | RW | 0xF05A0 | RX DMA {reserved,config}
ERX_DMADESCR1 | RW | 0xF05A4 | RX DMA {dst_stride[15:0],src_stride[15:0]}
ERX_DMADESCR2 | RW | 0xF05A8 | RX DMA {reserved,count[15:0]}
ERX_DMADESCR3 | RW | 0xF05B0 | RX DMA srcaddr[31:0]
ERX_DMADESCR5 | RW | 0xF05B4 | RX DMA dstaddr[31:0]
***************|****|*********|********************
ERX_MMU | -W | 0xE8000 | RX MMU table
@ -269,14 +257,14 @@ FIELD | DESCRIPTION
| 1: cclk driven from clkbypass[0] input
[3] | 0: lclk driven from internal PLL
| 1: lclk driven from clkbypass[1] input
[7:4] | 0000: cclk=pllclk/1
[7:4] | 0000: cclk=pllclk/1 (MAX)
| 0001: cclk=pllclk/2
| 0010: cclk=pllclk/4
| 0011: cclk=pllclk/8
| 0100: cclk=pllclk/16
| 0101: cclk=pllclk/32
| 0110: cclk=pllclk/64
| 0111: cclk=pllclk/128
| 0111: cclk=pllclk/128 (MIN)
| 1xxx: RESERVED
[11:8] | 0000: lclk=pllclk/1
| 0001: lclk=pllclk/2
@ -284,8 +272,8 @@ FIELD | DESCRIPTION
| 0011: lclk=pllclk/8
| 0100: lclk=pllclk/16
| 0101: lclk=pllclk/32
| 0110: lclk=pllclk/64
| 0111: lclk=pllclk/128
| 0110: lclk=pllclk/64 (not supported yet)
| 0111: lclk=pllclk/128 (not supported yet)
| 1xxx: RESERVED
[15:12] | PLL frequency (TBD)

4
elink/dv/dv_elink.v
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@ -151,8 +151,8 @@ module dv_elink(/*AUTOARG*/
assign elink0_txwr_packet[PW-1:0] = ext_packet[PW-1:0];
//TX Pushback
assign dut_rd_wait = elink0_txrd_wait | elink2_wait_out;
assign dut_wr_wait = elink0_txwr_wait | elink2_wait_out ;
assign dut_rd_wait = elink0_txrd_wait;// | elink2_wait_out;
assign dut_wr_wait = elink0_txwr_wait;// | elink2_wait_out ;
//Getting results back
assign dut_access = elink0_rxrr_access;

7
elink/dv/dv_elink_tb.v
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@ -72,13 +72,13 @@ module dv_elink_tb();
dv_elink.elink.ecfg.ecfg_rx_reg[4:0] = 5'h01;
`endif
reset = 1'b0; // at time 100 release reset
#1000
#4000
go = 1'b1;
#2000
#10000
`ifdef AUTO
go = 1'b0;
`endif
#80000
#20000
$finish;
end
@ -102,7 +102,6 @@ always @ (posedge clkstim)
transaction[MW-1:0] <= 'd0;
end
else if (go & ~(dut_wr_wait|dut_rd_wait))
//else if ((go & ~ext_access) | (go & ext_access & ~dut_wr_wait))
begin
`ifdef MANUAL
transaction[MW-1:0] <= stimarray[stim_addr];

16
elink/hdl/ecfg_rx.v
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@ -51,7 +51,7 @@ module ecfg_rx (/*AUTOARG*/
//registers
reg [31:0] ecfg_rx_reg;
reg [31:0] ecfg_base_reg;
reg [31:0] ecfg_offset_reg;
reg [8:0] ecfg_gpio_reg;
reg [2:0] ecfg_rx_status_reg;
reg [31:0] mi_dout;
@ -111,11 +111,11 @@ module ecfg_rx (/*AUTOARG*/
//###########################
always @ (posedge clk)
if(reset)
ecfg_base_reg[31:0] <='d0;
ecfg_offset_reg[31:0] <='d0;
else if (ecfg_base_write)
ecfg_base_reg[31:0] <=mi_din[31:0];
ecfg_offset_reg[31:0] <=mi_din[31:0];
assign remap_base[31:0] = ecfg_base_reg[31:0];
assign remap_base[31:0] = ecfg_offset_reg[31:0];
//###############################
//# DATA READBACK MUX
@ -128,10 +128,12 @@ module ecfg_rx (/*AUTOARG*/
`ERX_CFG: mi_dout[31:0] <= {ecfg_rx_reg[31:0]};
`ERX_GPIO: mi_dout[31:0] <= {23'b0, ecfg_gpio_reg[8:0]};
`ERX_STATUS: mi_dout[31:0] <= {16'b0, rx_status[15:3],ecfg_rx_status_reg[2:0]};
`ERX_OFFSET: mi_dout[31:0] <= {ecfg_base_reg[31:0]};
`ERX_OFFSET: mi_dout[31:0] <= {ecfg_offset_reg[31:0]};
default: mi_dout[31:0] <= 32'd0;
endcase
endcase // case (mi_addr[RFAW+1:2])
else
mi_dout[31:0] <= 32'd0;
endmodule // ecfg_rx
/*

4
elink/hdl/ecfg_tx.v
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@ -164,9 +164,7 @@ module ecfg_tx (/*AUTOARG*/
default: mi_dout[31:0] <= 32'd0;
endcase // case (mi_addr[RFAW+1:2])
else
begin
mi_dout[31:0] <= 32'd0;
end
mi_dout[31:0] <= 32'd0;
endmodule // ecfg_tx

36
elink/hdl/elink.v
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@ -134,9 +134,9 @@ module elink(/*AUTOARG*/
ecfg_clocks ecfg_clocks (.hard_reset (reset),
.clk (sys_clk),
.txwr_access_out (txwr_gated_access),//filter access to etx
/*AUTOINST*/
// Outputs
.txwr_wait (txwr_wait),
.soft_reset (soft_reset),
.ecfg_clk_settings (ecfg_clk_settings[15:0]),
// Inputs
@ -224,11 +224,12 @@ module elink(/*AUTOARG*/
.emrq_\(.*\) (esaxi_emrq_\1[]),
.emrr_\(.*\) (emaxi_emrr_\1[]),
.reset (elink_reset),
);
*/
defparam etx.ID=ID;
etx etx(
etx etx(.txwr_access (txwr_gated_access),
/*AUTOINST*/
// Outputs
.chipid (chipid[11:0]),
@ -256,7 +257,6 @@ module elink(/*AUTOARG*/
.txi_rd_wait_n (txi_rd_wait_n),
.txrd_access (txrd_access),
.txrd_packet (txrd_packet[PW-1:0]),
.txwr_access (txwr_access),
.txwr_packet (txwr_packet[PW-1:0]),
.txrr_access (txrr_access),
.txrr_packet (txrr_packet[PW-1:0]),
@ -267,25 +267,27 @@ module elink(/*AUTOARG*/
/***********************************************************/
/*fifo_cdc AUTO_TEMPLATE (.clk_in (tx_lclk_div4),
.clk_out (rx_lclk_div4),
.\(.*\)_in (etx_cfg_\1[]),
.\(.*\)_out (erx_cfg_\1[]),
.packet_in (etx_cfg_packet[PW-1:0]),
.packet_out (erx_cfg_packet[PW-1:0]),
.access_in (etx_cfg_access),
.access_out (erx_cfg_access),
.reset (elink_reset),
.wait_in (erx_cfg_wait),
.wait_out (etx_cfg_wait),
);
*/
fifo_cdc ecfg_cdc (/*AUTOINST*/
// Outputs
.wait_out (etx_cfg_wait), // Templated
.access_out (erx_cfg_access), // Templated
.packet_out (erx_cfg_packet[PW-1:0]), // Templated
// Inputs
.clk_in (tx_lclk_div4), // Templated
.clk_out (rx_lclk_div4), // Templated
.reset (elink_reset), // Templated
.access_in (etx_cfg_access), // Templated
.packet_in (etx_cfg_packet[PW-1:0]), // Templated
.wait_in (erx_cfg_wait)); // Templated
fifo_cdc #(.DW(104)) ecfg_cdc (/*AUTOINST*/
// Outputs
.wait_out (etx_cfg_wait), // Templated
.access_out (erx_cfg_access), // Templated
.packet_out (erx_cfg_packet[PW-1:0]), // Templated
// Inputs
.clk_in (tx_lclk_div4), // Templated
.clk_out (rx_lclk_div4), // Templated
.reset (elink_reset), // Templated
.access_in (etx_cfg_access), // Templated
.packet_in (etx_cfg_packet[PW-1:0]), // Templated
.wait_in (erx_cfg_wait)); // Templated
endmodule // elink

15
elink/hdl/elink_regmap.v
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@ -26,10 +26,9 @@
`define ERX_CFG 6'd0 //F0300-config
`define ERX_STATUS 6'd1 //F0304-status register
`define ERX_GPIO 6'd2 //F0308-sampled data
`define ERX_RR 6'd3 //F030C-read response address
`define ERX_OFFSET 6'd4 //F0310-memory base for remap
`define E_MAILBOXLO 6'd5 //F0314-reserved-->move?
`define E_MAILBOXHI 6'd6 //F0318-reserved
`define ERX_OFFSET 6'd3 //F030C-memory base for remap
`define E_MAILBOXLO 6'd4 //F0314-reserved-->move?
`define E_MAILBOXHI 6'd5 //F0318-reserved
//DMA (same numbering as in Epiphany, limit to 4 channels)
`define DMACFG 5'd0 //F0500/F0520
@ -40,11 +39,3 @@
`define DMAAUTO0 5'd5 //F0514/F0534
`define DMAAUTO1 5'd6 //F0518/F0538
`define DMASTATUS 5'd7 //F051C/F053c
//DMA descriptors (limited to 4 channels)
`define DMADESCR0 5'd0 //F0580/F05A0
`define DMADESCR1 5'd1 //F0584/F05A4
`define DMADESCR2 5'd2 //F0588/F05A8
`define DMADESCR3 5'd3 //F058c/F05Ac
`define DMADESCR4 5'd4 //F0590/F05B0
`define DMADESCR5 5'd5 //F0594/F05B4

85
elink/hdl/erx.v
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@ -59,6 +59,8 @@ module erx (/*AUTOARG*/
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire ecfg_access; // From erx_cfgif of ecfg_if.v
wire [PW-1:0] ecfg_packet; // From erx_cfgif of ecfg_if.v
wire edma_access; // From erx_dma of edma.v
wire edma_wait; // From erx_disty of erx_disty.v
wire emesh_remap_access; // From erx_remap of erx_remap.v
@ -75,7 +77,7 @@ module erx (/*AUTOARG*/
wire [63:0] mi_din; // From erx_cfgif of ecfg_if.v
wire [DW-1:0] mi_dma_dout; // From erx_dma of edma.v
wire mi_dma_en; // From erx_cfgif of ecfg_if.v
wire [31:0] mi_mailbox_dout; // From erx_mailbox of emailbox.v
wire [63:0] mi_mailbox_dout; // From erx_mailbox of emailbox.v
wire [DW-1:0] mi_mmu_dout; // From erx_mmu of emmu.v
wire mi_mmu_en; // From erx_cfgif of ecfg_if.v
wire mi_we; // From erx_cfgif of ecfg_if.v
@ -152,6 +154,10 @@ module erx (/*AUTOARG*/
.rx_lclk_div4 (rx_lclk_div4),
.rx_frame_par (rx_frame_par[7:0]),
.rx_data_par (rx_data_par[63:0]));
/**************************************************************/
/*ADDRESS REMPAPPING */
@ -227,14 +233,45 @@ module erx (/*AUTOARG*/
.emesh_packet_in (emesh_remap_packet[PW-1:0]), // Templated
.emesh_wait_in (erx_wait)); // Templated
/************************************************************/
/*EMAILBOX */
/************************************************************/
/*emailbox AUTO_TEMPLATE (
.mi_en (mi_cfg_en),
.mi_dout (mi_mailbox_dout[]),
.wr_clk (rx_lclk_div4),
.rd_clk (rx_lclk_div4),
.emesh_access (emmu_access),
.emesh_packet (emmu_packet[PW-1:0]),
);
*/
defparam erx_mailbox.ID=ID;
emailbox erx_mailbox(.mi_en (mi_cfg_en),
/*AUTOINST*/
// Outputs
.mi_dout (mi_mailbox_dout[63:0]), // Templated
.mailbox_full (mailbox_full),
.mailbox_not_empty(mailbox_not_empty),
// Inputs
.reset (reset),
.wr_clk (rx_lclk_div4), // Templated
.rd_clk (rx_lclk_div4), // Templated
.emesh_access (emmu_access), // Templated
.emesh_packet (emmu_packet[PW-1:0]), // Templated
.mi_we (mi_we),
.mi_addr (mi_addr[RFAW+1:0]),
.mi_din (mi_din[63:0]));
/************************************************************/
/* CONFIGURATION INTERFACE */
/************************************************************/
/*ecfg_if AUTO_TEMPLATE (
.wait_in (erx_cfg_wait),
.\(.*\)_in (erx_cfg_\1[]),
.\(.*\)_out (),
.\(.*\)_out (ecfg_\1[]),
.mi_dout0 ({32'b0,mi_cfg_dout[31:0]}),
.mi_dout1 ({32'b0,mi_dma_dout[31:0]}),
.mi_dout2 ({32'b0,mi_mmu_dout[31:0]}),
@ -246,15 +283,14 @@ module erx (/*AUTOARG*/
defparam erx_cfgif.RX=1;
ecfg_if erx_cfgif (/*AUTOINST*/
// Outputs
.wait_out (), // Templated
.mi_mmu_en (mi_mmu_en),
.mi_dma_en (mi_dma_en),
.mi_cfg_en (mi_cfg_en),
.mi_we (mi_we),
.mi_addr (mi_addr[14:0]),
.mi_din (mi_din[63:0]),
.access_out (), // Templated
.packet_out (), // Templated
.access_out (ecfg_access), // Templated
.packet_out (ecfg_packet[PW-1:0]), // Templated
// Inputs
.clk (rx_lclk_div4), // Templated
.reset (reset),
@ -319,31 +355,7 @@ module erx (/*AUTOARG*/
/************************************************************/
/*EMAILBOX */
/************************************************************/
/*emailbox AUTO_TEMPLATE (
.mi_en (mi_cfg_en),
.mi_dout (mi_mailbox_dout[]),
.wr_clk (rx_lclk_div4),
.rd_clk (rx_lclk_div4),
);
*/
//shares register space with ecfg_rx
emailbox erx_mailbox(.mi_en (mi_cfg_en),
/*AUTOINST*/
// Outputs
.mi_dout (mi_mailbox_dout[31:0]), // Templated
.mailbox_full (mailbox_full),
.mailbox_not_empty(mailbox_not_empty),
// Inputs
.reset (reset),
.wr_clk (rx_lclk_div4), // Templated
.rd_clk (rx_lclk_div4), // Templated
.mi_we (mi_we),
.mi_addr (mi_addr[19:0]),
.mi_din (mi_din[63:0]));
/************************************************************/
@ -381,7 +393,8 @@ module erx (/*AUTOARG*/
/*erx_disty AUTO_TEMPLATE (
//Inputs
.mmu_en (ecfg_rx_mmu_enable),
.clk (rx_lclk_div4),
.clk (rx_lclk_div4),
.ecfg_wait (erx_cfg_wait),
)
*/
@ -393,7 +406,7 @@ module erx (/*AUTOARG*/
.rx_rd_wait (rx_rd_wait),
.rx_wr_wait (rx_wr_wait),
.edma_wait (edma_wait),
.erx_cfg_wait (erx_cfg_wait),
.ecfg_wait (erx_cfg_wait), // Templated
.rxwr_fifo_access(rxwr_fifo_access),
.rxwr_fifo_packet(rxwr_fifo_packet[PW-1:0]),
.rxrd_fifo_access(rxrd_fifo_access),
@ -407,13 +420,12 @@ module erx (/*AUTOARG*/
.emmu_packet (emmu_packet[PW-1:0]),
.edma_access (edma_access),
.edma_packet (edma_packet[PW-1:0]),
.erx_cfg_access (erx_cfg_access),
.erx_cfg_packet (erx_cfg_packet[PW-1:0]),
.ecfg_access (ecfg_access),
.ecfg_packet (ecfg_packet[PW-1:0]),
.rxwr_fifo_wait (rxwr_fifo_wait),
.rxrd_fifo_wait (rxrd_fifo_wait),
.rxrr_fifo_wait (rxrr_fifo_wait));
/************************************************************/
/*FIFOs */
/*(for AXI 1. read request, 2. write, and 3. read response) */
@ -437,7 +449,6 @@ module erx (/*AUTOARG*/
);
*/
//Read request fifo (from Epiphany)
fifo_async #(.DW(104), .AW(5))

2
elink/hdl/erx_protocol.v
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@ -19,7 +19,7 @@ module erx_protocol (/*AUTOARG*/
parameter DW = 32;
parameter PW = 104;
parameter ID = 0;
parameter RFAW = 4;
// System reset input
input reset;

2
elink/hdl/etx_protocol.v
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@ -71,7 +71,7 @@ module etx_protocol (/*AUTOARG*/
chipid[11:0],20'b0,//dst
4'b0,2'b10,2'b11};//32bit write
else //initiate read
testpacket[PW-1:0]<={ID,12'hF03,`ERX_RR,2'b0,//src
testpacket[PW-1:0]<={ID,20'hD0000,//readback register
32'haaaaaaaa,//dummy data
chipid[11:0],20'b0,//read from address
4'b0,2'b10,2'b01};//32bit read