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Simplifying wait logic

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This commit is contained in:
Andreas Olofsson 2015-11-13 22:47:46 -05:00
parent c1beed9a13
commit 75710f25b7
1 changed files with 1 additions and 1 deletions
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emmu/hdl/emmu.v
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@ -129,7 +129,7 @@ module emmu (/*AUTOARG*/
//the pushback is needed stall async transmit path
always @ (posedge rd_clk)
if(~(emesh_wr_wait & write_in) & ~(emesh_rd_wait & ~write_in))
if(~(emesh_wr_wait | emesh_rd_wait))
begin
emesh_access_out <= emesh_access_in;
emesh_packet_reg[PW-1:0] <= emesh_packet_in[PW-1:0];