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Rename
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module emesh_memory(/*AUTOARG*/
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// Outputs
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wait_out, access_out, write_out, datamode_out, ctrlmode_out,
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dstaddr_out, data_out, srcaddr_out,
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// Inputs
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clk, reset, access_in, write_in, datamode_in, ctrlmode_in,
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dstaddr_in, data_in, srcaddr_in, wait_in
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);
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parameter DW = 32;
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parameter AW = 32;
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parameter MAW = 10;
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parameter LSB = $clog2(DW/8);
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//Basic Interface
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input clk;
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input reset;
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//incoming read/write
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input access_in;
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input write_in;
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input [1:0] datamode_in;
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input [3:0] ctrlmode_in;
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input [AW-1:0] dstaddr_in;
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input [DW-1:0] data_in;
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input [AW-1:0] srcaddr_in;
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output wait_out; //pushback
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//back to mesh (readback data)
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output access_out;
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output write_out;
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output [1:0] datamode_out;
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output [3:0] ctrlmode_out;
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output [AW-1:0] dstaddr_out;
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output [DW-1:0] data_out;
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output [AW-1:0] srcaddr_out;
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input wait_in; //pushback
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endmodule // emesh_memory
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// Local Variables:
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// verilog-library-directories:("." )
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// End:
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/*
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Copyright (C) 2014 Adapteva, Inc.
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Contributed by Andreas Olofsson <andreas@adapteva.com>
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This program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program (see the file COPYING). If not, see
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<http://www.gnu.org/licenses/>.
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*/
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