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GPIO: Add AXI GPIO module
Signed-off-by: Ola Jeppsson <ola@adapteva.com>
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Ola Jeppsson
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de8d7b7132
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186
src/gpio/hdl/axi_gpio.v
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186
src/gpio/hdl/axi_gpio.v
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//#############################################################################
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//# Purpose: AXI GPIO module #
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//#############################################################################
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//# Author: Ola Jeppsson #
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//# SPDX-License-Identifier: MIT #
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//#############################################################################
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module axi_gpio(/*AUTOARG*/
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// Outputs
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s_rd_packet, s_rd_access, s_axi_wready, s_axi_rvalid, s_axi_rresp,
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s_axi_rlast, s_axi_rid, s_axi_rdata, s_axi_bvalid, s_axi_bresp,
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s_axi_bid, s_axi_awready, s_axi_arready, gpio_out, gpio_irq,
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// Inputs
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s_axi_wvalid, s_axi_wstrb, s_axi_wlast, s_axi_wid, s_axi_wdata,
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s_axi_rready, s_axi_bready, s_axi_awvalid, s_axi_awsize,
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s_axi_awqos, s_axi_awprot, s_axi_awlock, s_axi_awlen, s_axi_awid,
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s_axi_awcache, s_axi_awburst, s_axi_awaddr, s_axi_arvalid,
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s_axi_arsize, s_axi_arqos, s_axi_arprot, s_axi_arlock, s_axi_arlen,
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s_axi_arid, s_axi_aresetn, s_axi_arcache, s_axi_arburst,
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s_axi_araddr, gpio_in, sys_nreset, sys_clk
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);
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//########################################################
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// INTERFACE
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//########################################################
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parameter AW = 32; // address width
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parameter PW = 2*AW+40; // packet width
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parameter ID = 12'h810; // addr[31:20] id
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parameter S_IDW = 12; // ID width for S_AXI
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parameter N = 24; // number of gpio pins
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//clk, reset
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input sys_nreset; // active low async reset
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input sys_clk; // system clock for AXI
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/*AUTOINPUT*/
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// Beginning of automatic inputs (from unused autoinst inputs)
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input [N-1:0] gpio_in; // To gpio of gpio.v
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input [31:0] s_axi_araddr; // To esaxi of esaxi.v
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input [1:0] s_axi_arburst; // To esaxi of esaxi.v
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input [3:0] s_axi_arcache; // To esaxi of esaxi.v
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input s_axi_aresetn; // To esaxi of esaxi.v
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input [S_IDW-1:0] s_axi_arid; // To esaxi of esaxi.v
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input [7:0] s_axi_arlen; // To esaxi of esaxi.v
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input s_axi_arlock; // To esaxi of esaxi.v
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input [2:0] s_axi_arprot; // To esaxi of esaxi.v
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input [3:0] s_axi_arqos; // To esaxi of esaxi.v
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input [2:0] s_axi_arsize; // To esaxi of esaxi.v
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input s_axi_arvalid; // To esaxi of esaxi.v
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input [31:0] s_axi_awaddr; // To esaxi of esaxi.v
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input [1:0] s_axi_awburst; // To esaxi of esaxi.v
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input [3:0] s_axi_awcache; // To esaxi of esaxi.v
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input [S_IDW-1:0] s_axi_awid; // To esaxi of esaxi.v
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input [7:0] s_axi_awlen; // To esaxi of esaxi.v
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input s_axi_awlock; // To esaxi of esaxi.v
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input [2:0] s_axi_awprot; // To esaxi of esaxi.v
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input [3:0] s_axi_awqos; // To esaxi of esaxi.v
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input [2:0] s_axi_awsize; // To esaxi of esaxi.v
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input s_axi_awvalid; // To esaxi of esaxi.v
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input s_axi_bready; // To esaxi of esaxi.v
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input s_axi_rready; // To esaxi of esaxi.v
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input [31:0] s_axi_wdata; // To esaxi of esaxi.v
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input [S_IDW-1:0] s_axi_wid; // To esaxi of esaxi.v
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input s_axi_wlast; // To esaxi of esaxi.v
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input [3:0] s_axi_wstrb; // To esaxi of esaxi.v
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input s_axi_wvalid; // To esaxi of esaxi.v
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// End of automatics
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/*AUTOOUTPUT*/
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// Beginning of automatic outputs (from unused autoinst outputs)
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output gpio_irq; // From gpio of gpio.v
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output [N-1:0] gpio_out; // From gpio of gpio.v
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output s_axi_arready; // From esaxi of esaxi.v
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output s_axi_awready; // From esaxi of esaxi.v
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output [S_IDW-1:0] s_axi_bid; // From esaxi of esaxi.v
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output [1:0] s_axi_bresp; // From esaxi of esaxi.v
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output s_axi_bvalid; // From esaxi of esaxi.v
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output [31:0] s_axi_rdata; // From esaxi of esaxi.v
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output [S_IDW-1:0] s_axi_rid; // From esaxi of esaxi.v
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output s_axi_rlast; // From esaxi of esaxi.v
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output [1:0] s_axi_rresp; // From esaxi of esaxi.v
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output s_axi_rvalid; // From esaxi of esaxi.v
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output s_axi_wready; // From esaxi of esaxi.v
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output s_rd_access; // From esaxi of esaxi.v
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output [PW-1:0] s_rd_packet; // From esaxi of esaxi.v
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// End of automatics
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/*AUTOWIRE*/
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/*AUTOREG*/
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wire gpio_wait_out;
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wire gpio_access_out;
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wire [PW-1:0] gpio_packet_out;
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wire gpio_access_in;
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wire [PW-1:0] gpio_packet_in;
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wire gpio_wait_in;
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wire [N-1:0] gpio_dir; /* don't output */
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gpio #(.AW(AW),.N(N))
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gpio(
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//Outputs
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.wait_out (gpio_wait_out),
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.access_out (gpio_access_out),
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.packet_out (gpio_packet_out[PW-1:0]),
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.gpio_dir (gpio_dir[N-1:0]),
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//Inputs
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.nreset (sys_nreset),
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.clk (sys_clk),
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.access_in (gpio_access_in),
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.packet_in (gpio_packet_in[PW-1:0]),
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.wait_in (gpio_wait_in),
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/*AUTOINST*/
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// Outputs
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.gpio_out (gpio_out[N-1:0]),
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.gpio_irq (gpio_irq),
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// Inputs
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.gpio_in (gpio_in[N-1:0]));
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//########################################################
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//AXI SLAVE
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//########################################################
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/*esaxi AUTO_TEMPLATE (//Stimulus
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.rr_\(.*\) (s_rr_\1[]),
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.rd_\(.*\) (s_rd_\1[]),
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.wr_\(.*\) (s_wr_\1[]),
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);
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*/
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esaxi #(.S_IDW(S_IDW))
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esaxi (.s_axi_aclk (sys_clk),
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.wr_access (gpio_access_in),
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.wr_packet (gpio_packet_in[PW-1:0]),
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.rr_wait (gpio_wait_in),
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.rd_wait (1'b0),
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.rr_access (gpio_access_out),
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.rr_packet (gpio_packet_out[PW-1:0]),
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.wr_wait (gpio_wait_out),
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/*AUTOINST*/
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// Outputs
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.rd_access (s_rd_access), // Templated
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.rd_packet (s_rd_packet[PW-1:0]), // Templated
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.s_axi_arready (s_axi_arready),
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.s_axi_awready (s_axi_awready),
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.s_axi_bid (s_axi_bid[S_IDW-1:0]),
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.s_axi_bresp (s_axi_bresp[1:0]),
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.s_axi_bvalid (s_axi_bvalid),
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.s_axi_rid (s_axi_rid[S_IDW-1:0]),
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.s_axi_rdata (s_axi_rdata[31:0]),
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.s_axi_rlast (s_axi_rlast),
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.s_axi_rresp (s_axi_rresp[1:0]),
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.s_axi_rvalid (s_axi_rvalid),
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.s_axi_wready (s_axi_wready),
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// Inputs
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.s_axi_aresetn (s_axi_aresetn),
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.s_axi_arid (s_axi_arid[S_IDW-1:0]),
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.s_axi_araddr (s_axi_araddr[31:0]),
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.s_axi_arburst (s_axi_arburst[1:0]),
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.s_axi_arcache (s_axi_arcache[3:0]),
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.s_axi_arlock (s_axi_arlock),
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.s_axi_arlen (s_axi_arlen[7:0]),
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.s_axi_arprot (s_axi_arprot[2:0]),
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.s_axi_arqos (s_axi_arqos[3:0]),
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.s_axi_arsize (s_axi_arsize[2:0]),
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.s_axi_arvalid (s_axi_arvalid),
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.s_axi_awid (s_axi_awid[S_IDW-1:0]),
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.s_axi_awaddr (s_axi_awaddr[31:0]),
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.s_axi_awburst (s_axi_awburst[1:0]),
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.s_axi_awcache (s_axi_awcache[3:0]),
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.s_axi_awlock (s_axi_awlock),
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.s_axi_awlen (s_axi_awlen[7:0]),
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.s_axi_awprot (s_axi_awprot[2:0]),
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.s_axi_awqos (s_axi_awqos[3:0]),
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.s_axi_awsize (s_axi_awsize[2:0]),
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.s_axi_awvalid (s_axi_awvalid),
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.s_axi_bready (s_axi_bready),
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.s_axi_rready (s_axi_rready),
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.s_axi_wid (s_axi_wid[S_IDW-1:0]),
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.s_axi_wdata (s_axi_wdata[31:0]),
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.s_axi_wlast (s_axi_wlast),
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.s_axi_wstrb (s_axi_wstrb[3:0]),
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.s_axi_wvalid (s_axi_wvalid));
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endmodule // axi_gpio
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// Local Variables:
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// verilog-library-directories:("." "../../axi/hdl" "../../common/hdl" "../../emesh/hdl")
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// End:
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