diff --git a/src/spi/hdl/spi.v b/src/spi/hdl/spi.v index 830e837..ca6687a 100644 --- a/src/spi/hdl/spi.v +++ b/src/spi/hdl/spi.v @@ -2,59 +2,43 @@ //# Purpose: SPI top (configurable as master or slave) # //############################################################################# //# Author: Andreas Olofsson # -//# License: MIT (see below) # +//# License: MIT (see LICENSE file in OH! repository) # //############################################################################# -module spi (/*AUTOARG*/ - // Outputs - spi_irq, access_out, packet_out, wait_out, m_sclk, m_mosi, m_ss, - s_miso, - // Inputs - nreset, clk, hw_en, access_in, packet_in, wait_in, m_miso, s_sclk, - s_mosi, s_ss - ); +module spi #( parameter AW = 32, // address width + parameter PW = 104, // packet size + parameter UREGS = 13 // number of user slave regs + ) + (//clk, reset, irq + input nreset, // asynch active low reset + input clk, // core clock + input hw_en, // block enable pin + output spi_irq, // interrupt output + //packet from core + input access_in, // access from core + input [PW-1:0] packet_in, // packet from core + input wait_in, // pushback from io + //packet to core + output access_out, // access to core + output [PW-1:0] packet_out, // packet to core + output wait_out, // pushback from core + //master io interface + output m_sclk, // master clock + output m_mosi, // master output + output m_ss, // slave select + input m_miso, // master input + //slave io interface + input s_sclk, // slave clock + input s_mosi, // slave input + input s_ss, // slave select + output s_miso // slave output + ); - //################################################################## - //# INTERFACE - //################################################################## - - parameter AW = 32; // data width of fifo - parameter PW = 2*AW+40; // packet size - parameter UREGS = 13; // number of user slave regs - - //clk, reset, irq - input nreset; // asynch active low reset - input clk; // core clock - input hw_en; // block enable pin - - //interrupt output - output spi_irq; // interrupt output - - //packet from core - input access_in; // access from core - input [PW-1:0] packet_in; // packet from core - input wait_in; // pushback from io - - //packet to core - output access_out; // access to core - output [PW-1:0] packet_out; // packet to core - output wait_out; // pushback from core - - //master io interface - output m_sclk; // master clock - output m_mosi; // master output - output m_ss; // slave select - input m_miso; // master input - - //slave io interface - input s_sclk; // slave clock - input s_mosi; // slave input - input s_ss; // slave select - output s_miso; // slave output + //############### + //# LOCAL WIRES + //############### /*AUTOINPUT*/ - // End of automatics - /*AUTOWIRE*/ // Beginning of automatic wires (for undeclared instantiated-module outputs) wire m_access_out; // From spi_master of spi_master.v @@ -78,7 +62,8 @@ module spi (/*AUTOARG*/ ); */ - spi_master #(.AW(AW)) + spi_master #(.AW(AW), + .PW(PW)) spi_master (/*AUTOINST*/ // Outputs .sclk (m_sclk), // Templated @@ -110,6 +95,7 @@ module spi (/*AUTOARG*/ */ spi_slave #(.AW(AW), + .PW(PW), .UREGS(UREGS)) spi_slave (/*AUTOINST*/ // Outputs @@ -137,7 +123,8 @@ module spi (/*AUTOARG*/ assign wait_out = s_wait_out | m_wait_out; emesh_mux #(.N(2), - .AW(AW)) + .AW(AW), + .PW(PW)) emesh_mux (// Outputs .wait_out (), .access_out (access_out), @@ -153,27 +140,3 @@ endmodule // spi // verilog-library-directories:("." "../hdl" "../../emesh/hdl") // End: -////////////////////////////////////////////////////////////////////////////// -// The MIT License (MIT) // -// // -// Copyright (c) 2015-2016, Adapteva, Inc. // -// // -// Permission is hereby granted, free of charge, to any person obtaining a // -// copy of this software and associated documentation files (the "Software")// -// to deal in the Software without restriction, including without limitation// -// the rights to use, copy, modify, merge, publish, distribute, sublicense, // -// and/or sell copies of the Software, and to permit persons to whom the // -// Software is furnished to do so, subject to the following conditions: // -// // -// The above copyright notice and this permission notice shall be included // -// in all copies or substantial portions of the Software. // -// // -// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS // -// OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF // -// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. // -// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY // -// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT// -// OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR // -// THE USE OR OTHER DEALINGS IN THE SOFTWARE. // -// // -////////////////////////////////////////////////////////////////////////////// diff --git a/src/spi/hdl/spi_master.v b/src/spi/hdl/spi_master.v index 12a07e0..b1d12ad 100644 --- a/src/spi/hdl/spi_master.v +++ b/src/spi/hdl/spi_master.v @@ -1,44 +1,38 @@ //############################################################################# -//# Purpose: SPI master (configurable) # +//# Purpose: SPI master # //############################################################################# //# Author: Andreas Olofsson # -//# License: MIT (see below) # +//# License: MIT (see LICENSE file in OH! repository) # //############################################################################# -module spi_master(/*AUTOARG*/ - // Outputs - sclk, mosi, ss, wait_out, access_out, packet_out, - // Inputs - clk, nreset, hw_en, miso, access_in, packet_in, wait_in - ); - - //parameters - parameter DEPTH = 32; // fifo depth - parameter REGS = 16; // total regs - parameter AW = 32; // addresss width - localparam PW = (2*AW+40); // packet width - - //clk,reset, cfg - input clk; // core clock - input nreset; // async active low reset - input hw_en; // hardware enable pin +module spi_master # ( parameter DEPTH = 32, // fifo depth + parameter REGS = 16, // total # of regs + parameter AW = 32, // addresss width + parameter PW = 104 // packet width + ) + ( + //clk,reset, cfg + input clk, // core clock + input nreset, // async active low reset + input hw_en, // hardware enable pin + //IO interface + output sclk, // spi clock + output mosi, // slave input + output ss, // slave select + input miso, // slave output + //packet to transmit + input access_in, // access from core + input [PW-1:0] packet_in, // data to core + output wait_out, // pushback from spi register + //return packet + output access_out, // readback access + output [PW-1:0] packet_out, // packet from spi register + input wait_in // pushback by core + ); - //IO interface - output sclk; // spi clock - output mosi; // slave input - output ss; // slave select - input miso; // slave output - - //packet to transmit - input access_in; // access from core - input [PW-1:0] packet_in; // data to core - output wait_out; // pushback from spi register - - //return packet - output access_out; // readback access - output [PW-1:0] packet_out; // packet from spi register - input wait_in; // pushback by core - + //############### + //# LOCAL WIRES + //############### /*AUTOINPUT*/ /*AUTOOUTPUT*/ @@ -63,7 +57,8 @@ module spi_master(/*AUTOARG*/ //# Master control registers //##################################################### - spi_master_regs #(.AW(AW)) + spi_master_regs #(.AW(AW), + .PW(PW)) spi_master_regs (/*AUTOINST*/ // Outputs .cpol (cpol), @@ -97,6 +92,7 @@ module spi_master(/*AUTOARG*/ */ spi_master_fifo #(.AW(AW), + .PW(PW), .DEPTH(DEPTH)) spi_master_fifo( /*AUTOINST*/ @@ -117,7 +113,7 @@ module spi_master(/*AUTOARG*/ //# SPI IO (8 bit) //##################################################### - spi_master_io #(.AW(AW)) + spi_master_io spi_master_io (/*AUTOINST*/ // Outputs .spi_state (spi_state[1:0]), @@ -140,28 +136,3 @@ module spi_master(/*AUTOARG*/ endmodule // spi_master - -////////////////////////////////////////////////////////////////////////////// -// The MIT License (MIT) // -// // -// Copyright (c) 2015-2016, Adapteva, Inc. // -// // -// Permission is hereby granted, free of charge, to any person obtaining a // -// copy of this software and associated documentation files (the "Software")// -// to deal in the Software without restriction, including without limitation// -// the rights to use, copy, modify, merge, publish, distribute, sublicense, // -// and/or sell copies of the Software, and to permit persons to whom the // -// Software is furnished to do so, subject to the following conditions: // -// // -// The above copyright notice and this permission notice shall be included // -// in all copies or substantial portions of the Software. // -// // -// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS // -// OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF // -// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. // -// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY // -// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT// -// OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR // -// THE USE OR OTHER DEALINGS IN THE SOFTWARE. // -// // -////////////////////////////////////////////////////////////////////////////// diff --git a/src/spi/hdl/spi_master_fifo.v b/src/spi/hdl/spi_master_fifo.v index 54bff48..83c588d 100644 --- a/src/spi/hdl/spi_master_fifo.v +++ b/src/spi/hdl/spi_master_fifo.v @@ -1,46 +1,40 @@ +//############################################################################# +//# Purpose: SPI Master Transmit Fifo # +//############################################################################# +//# Author: Andreas Olofsson # +//# License: MIT (see LICENSE file in OH! repository) # +//############################################################################# + `include "spi_regmap.vh" -module spi_master_fifo (/*AUTOARG*/ - // Outputs - fifo_prog_full, wait_out, fifo_empty, fifo_dout, - // Inputs - clk, nreset, spi_en, access_in, packet_in, fifo_read - ); - //##################################################################### - //# INTERFACE - //##################################################################### - - //parameters - parameter DEPTH = 16; // fifo entries - parameter AW = 32; // architecture address width - parameter SW = 8; // output packet width - localparam PW = 2*AW+40; // input packet width - parameter FAW = $clog2(DEPTH); // fifo address width - parameter SRW = $clog2(PW/SW); // serializer cycle count width +module spi_master_fifo #( parameter DEPTH = 16, // fifo entries + parameter AW = 32, // address width + parameter PW = 104, // input packet width + parameter SW = 8, // io packet width + parameter FAW = $clog2(DEPTH), // fifo address width + parameter SRW = $clog2(PW/SW) // serialization factor + ) + ( + //clk,reset, cfg + input clk, // clk + input nreset, // async active low reset + input spi_en, // spi enable + output fifo_prog_full, // fifo full indicator for status + // Incoming interface + input access_in, // access by core + input [PW-1:0] packet_in, // packet from core + output wait_out, // pushback to core + // IO interface + input fifo_read, // pull a byte to IO + output fifo_empty, // fifo is empty + output [SW-1:0] fifo_dout // byte for IO + ); - //clk,reset, cfg - input clk; // clk - input nreset; // async active low reset - input spi_en; // spi enable - output fifo_prog_full; // fifo full indicator for status - - // Incoming interface - input access_in; // access by core - input [PW-1:0] packet_in; // packet from core - output wait_out; // pushback to core - - // IO interface - input fifo_read; // pull a byte to IO - output fifo_empty; // fifo is empty - output [SW-1:0] fifo_dout; // byte for IO - - //################################## - //# BODY - //################################## - + //############### + //# LOCAL WIRES + //############### wire [7:0] datasize; wire [PW-1:0] tx_data; wire [SW-1:0] fifo_din; - /*AUTOWIRE*/ // Beginning of automatic wires (for undeclared instantiated-module outputs) wire [4:0] ctrlmode_in; // From p2e of packet2emesh.v @@ -55,7 +49,8 @@ module spi_master_fifo (/*AUTOARG*/ //# DECODE //################################### - packet2emesh #(.AW(AW)) + packet2emesh #(.AW(AW), + .PW(PW)) p2e (/*AUTOINST*/ // Outputs .write_in (write_in), diff --git a/src/spi/hdl/spi_master_io.v b/src/spi/hdl/spi_master_io.v index c86423d..1dad7d6 100644 --- a/src/spi/hdl/spi_master_io.v +++ b/src/spi/hdl/spi_master_io.v @@ -1,57 +1,39 @@ //############################################################################# -//# Purpose: SPI slave IO and statemachine # +//# Purpose: SPI master IO state-machine # //############################################################################# //# Author: Andreas Olofsson # -//# License: MIT (see below) # +//# License: MIT (see LICENSE file in OH! repository) # //############################################################################# - -module spi_master_io(/*AUTOARG*/ - // Outputs - spi_state, fifo_read, rx_data, rx_access, sclk, mosi, ss, - // Inputs - clk, nreset, cpol, cpha, lsbfirst, clkdiv_reg, fifo_dout, - fifo_empty, miso +module spi_master_io + ( + //clk, reset, cfg + input clk, // core clock + input nreset, // async active low reset + input cpol, // cpol + input cpha, // cpha + input lsbfirst, // send lsbfirst + input [7:0] clkdiv_reg, // baudrate + output [1:0] spi_state, // current spi tx state + // data to transmit + input [7:0] fifo_dout, // data payload + input fifo_empty, // + output fifo_read, // read new byte + // receive data (for sregs) + output [63:0] rx_data, // rx data + output rx_access, // transfer done + // IO interface + output sclk, // spi clock + output mosi, // slave input + output ss, // slave select + input miso // slave output ); - //################################# - //# INTERFACE - //################################# - - //parameters - parameter REGS = 16; // total regs (16/32/64) - parameter AW = 32; // address width - localparam PW = (2*AW+40); // packet width - - //clk, reset, cfg - input clk; // core clock - input nreset; // async active low reset - - //cfg - input cpol; // cpol - input cpha; // cpha - input lsbfirst; // send lsbfirst - input [7:0] clkdiv_reg; // baudrate - output [1:0] spi_state; // current spi tx state - - //data to transmit - input [7:0] fifo_dout; // data payload - input fifo_empty; // - output fifo_read; // read new byte - - //receive data (for sregs) - output [63:0] rx_data; // rx data - output rx_access; // transfer done - - //IO interface - output sclk; // spi clock - output mosi; // slave input - output ss; // slave select - input miso; // slave output - + //############### + //# LOCAL WIRES + //############### reg [1:0] spi_state; reg fifo_empty_reg; reg load_byte; - wire [7:0] data_out; wire [15:0] clkphase0; @@ -178,35 +160,9 @@ module spi_master_io(/*AUTOARG*/ .lsbfirst (lsbfirst), // shift direction .shift (shift)); // shift data -endmodule // spi_slave_io - +endmodule // spi_master_io // Local Variables: // verilog-library-directories:("." "../../common/hdl" "../../emesh/hdl") // End: -/////////////////////////////////////////////////////////////////////////////// -// The MIT License (MIT) // -// // -// Copyright (c) 2015-2016, Adapteva, Inc. // -// // -// Permission is hereby granted, free of charge, to any person obtaining a // -// copy of this software and associated documentation files (the "Software") // -// to deal in the Software without restriction, including without limitation // -// the rights to use, copy, modify, merge, publish, distribute, sublicense, // -// and/or sell copies of the Software, and to permit persons to whom the // -// Software is furnished to do so, subject to the following conditions: // -// // -// The above copyright notice and this permission notice shall be included // -// in all copies or substantial portions of the Software. // -// // -// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS // -// OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF // -// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. // -// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY // -// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT // -// OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR // -// THE USE OR OTHER DEALINGS IN THE SOFTWARE. // -// // -/////////////////////////////////////////////////////////////////////////////// - diff --git a/src/spi/hdl/spi_master_regs.v b/src/spi/hdl/spi_master_regs.v index 2f86a03..fbd092c 100644 --- a/src/spi/hdl/spi_master_regs.v +++ b/src/spi/hdl/spi_master_regs.v @@ -1,60 +1,45 @@ - //############################################################################# -//# Purpose: SPI master (configurable) # +//# Purpose: SPI master Registers # //############################################################################# //# Author: Andreas Olofsson # -//# License: MIT (see below) # +//# License: MIT (see LICENSE file in OH! repository) # //############################################################################# `include "spi_regmap.vh" -module spi_master_regs (/*AUTOARG*/ - // Outputs - cpol, cpha, lsbfirst, spi_en, clkdiv_reg, wait_out, access_out, - packet_out, - // Inputs - clk, nreset, hw_en, rx_data, rx_access, spi_state, fifo_prog_full, - fifo_wait, access_in, packet_in, wait_in - ); - - //parameters - parameter CLKDIV = 1; // default clkdiv - parameter PSIZE = 0; // default is 32 bits - parameter AW = 32; // addresss width - localparam PW = (2*AW+40); // packet width - - //clk,reset, cfg - input clk; // core clock - input nreset; // async active low reset - input hw_en; // block enable pin - - //io interface - input [63:0] rx_data; // rx data - input rx_access; // rx access pulse - - //control - output cpol; // clk polarity (default is 0) - output cpha; // clk phase shift (default is 0) - output lsbfirst; // send lsbfirst - output spi_en; // enable transmitter - output [7:0] clkdiv_reg; // baud rate setting - input [1:0] spi_state; // transmit state - input fifo_prog_full; // fifo reached half/full - input fifo_wait; // tx transfer wait - - //packet to transmit - input access_in; // access from core - input [PW-1:0] packet_in; // data to core - output wait_out; // pushback from spi master - - //return packet - output access_out; // writeback from spi - output [PW-1:0] packet_out; // writeback data from spi - input wait_in; // pushback by core - - //######################################################## - //# BODY - //######################################################## +module spi_master_regs # (parameter CLKDIV = 1, // default clkdiv + parameter AW = 32, // addresss width + parameter PW = 104 // packet width + ) + ( + //clk,reset, cfg + input clk, // core clock + input nreset, // async active low reset + input hw_en, // block enable pin + //io interface + input [63:0] rx_data, // rx data + input rx_access, // rx access pulse + //control + output cpol, // clk polarity (default is 0) + output cpha, // clk phase shift (default is 0) + output lsbfirst, // send lsbfirst + output spi_en, // enable transmitter + output [7:0] clkdiv_reg, // baud rate setting + input [1:0] spi_state, // transmit state + input fifo_prog_full, // fifo reached half/full + input fifo_wait, // tx transfer wait + //packet to transmit + input access_in, // access from core + input [PW-1:0] packet_in, // data to core + output wait_out, // pushback from spi master + //return packet + output access_out, // writeback from spi + output [PW-1:0] packet_out, // writeback data from spi + input wait_in // pushback by core + ); + //############### + //# LOCAL WIRES + //############### reg [7:0] config_reg; reg [7:0] status_reg; reg [7:0] clkdiv_reg; @@ -84,7 +69,8 @@ module spi_master_regs (/*AUTOARG*/ //# DECODE //#################################### - packet2emesh #(.AW(AW)) + packet2emesh #(.AW(AW), + .PW(PW)) pe2 (/*AUTOINST*/ // Outputs .write_in (write_in), @@ -192,7 +178,8 @@ module spi_master_regs (/*AUTOARG*/ //TODO: fix! assign wait_out = fifo_wait; - emesh2packet #(.AW(AW)) + emesh2packet #(.AW(AW), + .PW(PW)) e2p (.write_out (1'b1), .srcaddr_out ({(AW){1'b0}}), .data_out (reg_rdata[AW-1:0]), diff --git a/src/spi/hdl/spi_regmap.vh b/src/spi/hdl/spi_regmap.vh index 667c824..3709031 100644 --- a/src/spi/hdl/spi_regmap.vh +++ b/src/spi/hdl/spi_regmap.vh @@ -1,3 +1,10 @@ +//############################################################################# +//# Purpose: SPI Register Map # +//############################################################################# +//# Author: Andreas Olofsson # +//# License: MIT (see LICENSE file in OH! repository) # +//############################################################################# + //8 bit registers [5:0] `ifndef SPI_REGMAP_VH_ `define SPI_REGMAP_VH_ diff --git a/src/spi/hdl/spi_slave.v b/src/spi/hdl/spi_slave.v index d481ab2..4b5c3ef 100644 --- a/src/spi/hdl/spi_slave.v +++ b/src/spi/hdl/spi_slave.v @@ -1,50 +1,40 @@ //############################################################################# -//# Purpose: SPI slave module # +//# Purpose: SPI slave # //############################################################################# //# Author: Andreas Olofsson # -//# License: MIT (see below) # +//# License: MIT (see LICENSE file in OH! repository) # //############################################################################# -module spi_slave(/*AUTOARG*/ - // Outputs - spi_regs, spi_irq, miso, access_out, packet_out, wait_out, - // Inputs - clk, nreset, hw_en, sclk, mosi, ss, wait_in, access_in, packet_in - ); - - //parameters - parameter UREGS = 13; // total spi slave regs - parameter AW = 32; // addresss width - localparam PW = (2*AW+40); // packet width - - //clk,reset, cfg - input clk; // core clock - input nreset; // async active low reset - input hw_en; // block enbale pin - output [511:0] spi_regs; // all registers for control - output spi_irq; // interrupt +module spi_slave #( parameter UREGS = 13, // number of spi slave regs + parameter AW = 32, // addresss width + parameter PW = 104 // packet width + ) + ( + //clk,reset, cfg + input clk, // core clock + input nreset, // async active low reset + input hw_en, // block enbale pin + output [511:0] spi_regs, // all registers for control + output spi_irq, // interrupt + //IO interface + input sclk, // spi clock + input mosi, // slave input + input ss, // slave select + output miso, // slave output + // read request to core + output access_out, // valid transaction + output [PW-1:0] packet_out, // data to core (from spi port) + input wait_in, // pushback from core (not implemented) + // return from core + input access_in, // read response from core + input [PW-1:0] packet_in, // read response packet from core + output wait_out // pushback (not used) + ); - //IO interface - input sclk; // spi clock - input mosi; // slave input - input ss; // slave select - output miso; // slave output - - - // read request to core - output access_out; // valid transaction - output [PW-1:0] packet_out; // data to core (from spi port) - input wait_in; // pushback from core (not implemented) - - // return from core - input access_in; // read response from core - input [PW-1:0] packet_in; // read response packet from core - output wait_out; // pushback (not used) - + //############### + //# LOCAL WIRES + //############### /*AUTOINPUT*/ - - // End of automatics - /*AUTOWIRE*/ // Beginning of automatic wires (for undeclared instantiated-module outputs) wire cpha; // From spi_slave_regs of spi_slave_regs.v @@ -60,6 +50,7 @@ module spi_slave(/*AUTOARG*/ // End of automatics spi_slave_regs #(.AW(AW), + .PW(PW), .UREGS(UREGS)) spi_slave_regs (/*AUTOINST*/ // Outputs @@ -84,7 +75,7 @@ module spi_slave(/*AUTOARG*/ .packet_in (packet_in[PW-1:0])); - spi_slave_io #(.AW(AW)) + spi_slave_io #(.PW(PW)) spi_slave_io (/*AUTOINST*/ // Outputs .miso (miso), @@ -109,28 +100,3 @@ module spi_slave(/*AUTOARG*/ endmodule // spi_slave - -////////////////////////////////////////////////////////////////////////////// -// The MIT License (MIT) // -// // -// Copyright (c) 2015-2016, Adapteva, Inc. // -// // -// Permission is hereby granted, free of charge, to any person obtaining a // -// copy of this software and associated documentation files (the "Software")// -// to deal in the Software without restriction, including without limitation// -// the rights to use, copy, modify, merge, publish, distribute, sublicense, // -// and/or sell copies of the Software, and to permit persons to whom the // -// Software is furnished to do so, subject to the following conditions: // -// // -// The above copyright notice and this permission notice shall be included // -// in all copies or substantial portions of the Software. // -// // -// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS // -// OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF // -// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. // -// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY // -// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT// -// OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR // -// THE USE OR OTHER DEALINGS IN THE SOFTWARE. // -// // -////////////////////////////////////////////////////////////////////////////// diff --git a/src/spi/hdl/spi_slave_io.v b/src/spi/hdl/spi_slave_io.v index 997a635..a85876a 100644 --- a/src/spi/hdl/spi_slave_io.v +++ b/src/spi/hdl/spi_slave_io.v @@ -1,67 +1,49 @@ //############################################################################# -//# Purpose: SPI slave IO and statemachine # +//# Purpose: SPI slave IO state-machine # //############################################################################# //# Author: Andreas Olofsson # -//# License: MIT (see below) # +//# License: MIT (see LICENSE file in OH! repository) # //############################################################################# `include "spi_regmap.vh" -module spi_slave_io(/*AUTOARG*/ - // Outputs - miso, spi_clk, spi_write, spi_addr, spi_wdata, spi_rdata, - access_out, packet_out, - // Inputs - sclk, mosi, ss, spi_en, cpol, cpha, lsbfirst, clk, nreset, wait_in - ); +module spi_slave_io #( parameter PW = 104 // packet width + ) + ( + //IO interface + input sclk, // slave clock + input mosi, // slave input + input ss, // slave select + output miso, // slave output + //Control + input spi_en, // spi enable + input cpol, // cpol + input cpha, // cpha + input lsbfirst, // lsbfirst + //register file interface + output spi_clk, // spi clock for regfile + output spi_write, // regfile write + output [5:0] spi_addr, // regfile addres + output [7:0] spi_wdata, // data for regfile + output [7:0] spi_rdata, // data for regfile + //core interface (synced to core clk) + input clk, // core clock + input nreset, // async active low reset + output access_out, // read or write core command + output [PW-1:0] packet_out, // packet + input wait_in // temporary pushback + ); - //################################# - //# INTERFACE - //################################# - - //parameters - parameter SREGS = 16; // total regs (16/32/64) - parameter AW = 32; // address width - localparam PW = (2*AW+40); // packet width + //############### + //# LOCAL WIRES + //############### + reg [1:0] spi_state; + reg [7:0] bit_count; + reg [7:0] command_reg; + reg access_out; + reg fetch_command; + wire [7:0] rx_data; + wire [63:0] tx_data; - //IO interface - input sclk; // slave clock - input mosi; // slave input - input ss; // slave select - output miso; // slave output - - //Control - input spi_en; // spi enable - input cpol; // cpol - input cpha; // cpha - input lsbfirst; // lsbfirst - - //register file interface - output spi_clk; // spi clock for regfile - output spi_write; // regfile write - output [5:0] spi_addr; // regfile addres - output [7:0] spi_wdata; // data for regfile - output [7:0] spi_rdata; // data for regfile - - //core interface (synced to core clk) - input clk; // core clock - input nreset; // async active low reset - output access_out; // read or write core command - output [PW-1:0] packet_out; // packet - input wait_in; // temporary pushback - - //################################# - //# BODY - //################################# - - reg [1:0] spi_state; - reg [7:0] bit_count; - reg [7:0] command_reg; - reg access_out; - reg fetch_command; - - wire [7:0] rx_data; - wire [63:0] tx_data; - //################################# //# STATE MACHINE //################################# diff --git a/src/spi/hdl/spi_slave_regs.v b/src/spi/hdl/spi_slave_regs.v index 89ad484..118549f 100644 --- a/src/spi/hdl/spi_slave_regs.v +++ b/src/spi/hdl/spi_slave_regs.v @@ -1,65 +1,53 @@ //############################################################################# -//# Purpose: SPI slave port register file # +//# Purpose: SPI slave register file # //############################################################################# //# Author: Andreas Olofsson # -//# License: MIT (see below) # +//# License: MIT (see LICENSE file in OH! repository) # //############################################################################# `include "spi_regmap.vh" -module spi_slave_regs (/*AUTOARG*/ - // Outputs - spi_rdata, spi_en, cpol, cpha, lsbfirst, irq_en, spi_regs, - wait_out, - // Inputs - clk, nreset, hw_en, spi_clk, spi_wdata, spi_write, spi_addr, - access_out, access_in, packet_in - ); - - //parameters - parameter UREGS = 13; // number of user regs (max 48) - parameter CHIPID = 0; // reset chipid value - parameter AW = 32; // address width - localparam PW = (2*AW+40); // packet width - localparam SREGS = UREGS+32; // total regs - +module spi_slave_regs #( parameter UREGS = 13, // # of user regs (max 48) + parameter SREGS = UREGS+32,// total regs + parameter AW = 32, // address width + parameter PW = 104 // packet width + ) + ( // clk, rest, chipid - input clk; // core clock - input nreset; // asych active low - input hw_en; // block enable pin - + input clk, // core clock + input nreset, // asych active low + input hw_en, // block enable pin // sclk io domain - input spi_clk; // slave clock - input [7:0] spi_wdata; // slave write data in (for write) - input spi_write; // slave write - input [5:0] spi_addr; // slave write addr (64 regs) - output [7:0] spi_rdata; // slave read data - + input spi_clk, // slave clock + input [7:0] spi_wdata, // slave write data in (for write) + input spi_write, // slave write + input [5:0] spi_addr, // slave write addr (64 regs) + output [7:0] spi_rdata, // slave read data // cfg bits - output spi_en; // enable spi - output cpol; // clk polarity (default is 0) - output cpha; // clk phase shift (default is 0) - output lsbfirst; // send lsbfirst - output irq_en; // interrupt enable - output [511:0] spi_regs; // all regs concatenated for easy read - + output spi_en, // enable spi + output cpol, // clk polarity (default is 0) + output cpha, // clk phase shift (default is 0) + output lsbfirst, // send lsbfirst + output irq_en, // interrupt enable + output [511:0] spi_regs, // all regs concatenated for easy read // split transaction for core clock domain - input access_out; // signal used to clear status - input access_in; - input [PW-1:0] packet_in; // writeback data - output wait_out; // 0 - - //regs + input access_out, // signal used to clear status + input access_in, + input [PW-1:0] packet_in, // writeback data + output wait_out + ); + + //############### + //# LOCAL WIRES + //############### reg [7:0] spi_config; reg [7:0] spi_status; reg [7:0] spi_cmd; reg [7:0] spi_psize; - reg [63:0] core_regs; reg [7:0] user_regs[UREGS-1:0]; reg [511:0] spi_regs; wire [63:0] core_data; integer i; - /*AUTOWIRE*/ // Beginning of automatic wires (for undeclared instantiated-module outputs) wire [4:0] ctrlmode_in; // From pe2 of packet2emesh.v @@ -166,32 +154,6 @@ module spi_slave_regs (/*AUTOARG*/ assign spi_rdata[7:0] = spi_regs[8*spi_addr[5:0]+:8]; endmodule // spi_slave_regs - // Local Variables: // verilog-library-directories:("." "../../common/hdl" "../../emesh/hdl") // End: - -////////////////////////////////////////////////////////////////////////////// -// The MIT License (MIT) // -// // -// Copyright (c) 2015-2016, Adapteva, Inc. // -// // -// Permission is hereby granted, free of charge, to any person obtaining a // -// copy of this software and associated documentation files (the "Software")// -// to deal in the Software without restriction, including without limitation// -// the rights to use, copy, modify, merge, publish, distribute, sublicense, // -// and/or sell copies of the Software, and to permit persons to whom the // -// Software is furnished to do so, subject to the following conditions: // -// // -// The above copyright notice and this permission notice shall be included // -// in all copies or substantial portions of the Software. // -// // -// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS // -// OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF // -// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. // -// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY // -// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT// -// OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR // -// THE USE OR OTHER DEALINGS IN THE SOFTWARE. // -// // -//////////////////////////////////////////////////////////////////////////////