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Fixing up issues with database reorg

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- Not sure where the prog_full issue popped up from. (sign of disorganized databsae)
-
This commit is contained in:
Andreas Olofsson 2015-11-30 15:07:28 -05:00
parent 19fa611bb9
commit 7b8460b145
14 changed files with 26 additions and 170 deletions
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3
common/fpga/create_ip.tcl
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@ -3,6 +3,7 @@
###########################################################
create_project -force $design $projdir -part $partname
set_property target_language Verilog [current_project]
set_property source_mgmt_mode None [current_project]
###########################################################
# Create filesets and add files to project
@ -15,6 +16,8 @@ if {[string equal [get_filesets -quiet sources_1] ""]} {
add_files -norecurse -fileset [get_filesets sources_1] $hdl_files
set_property top $design [get_filesets sources_1]
#CONSTRAINTS
if {[string equal [get_filesets -quiet constraints_1] ""]} {
create_fileset -constrset constraints_1

2
common/hdl/oh_csa32.v
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@ -1,4 +1,4 @@
//CSA3:2 Compressor
/CSA3:2 Compressor
module oh_csa32 (/*AUTOARG*/
// Outputs
c, s,

1
common/hdl/oh_csa34to2.v
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@ -167,3 +167,4 @@ module oh_csa34to2 (/*AUTOARG*/
endmodule // oh_csa34to2

66
common/hdl/oh_decoder5.v
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@ -1,66 +0,0 @@
// #
// # This block converts encoded 5 bits
// # into their decoded form of 32 bits
// # In addition to the five bits encoded
// # input, the block gets enable signal
// # which results in all zeros on the
// # output if disabled.
// #
module oh_decoder5 (/*AUTOARG*/
// Outputs
dec_out,
// Inputs
enc_in, enc_val
);
input [5:0] enc_in;
input enc_val;
output [31:0] dec_out;
reg [31:0] dec_out;
always @ (*)
begin
casez ({enc_val,enc_in[4:0]})
6'b1_00000 : dec_out[31:0] = 32'b00000000000000000000000000000001;
6'b1_00001 : dec_out[31:0] = 32'b00000000000000000000000000000010;
6'b1_00010 : dec_out[31:0] = 32'b00000000000000000000000000000100;
6'b1_00011 : dec_out[31:0] = 32'b00000000000000000000000000001000;
6'b1_00100 : dec_out[31:0] = 32'b00000000000000000000000000010000;
6'b1_00101 : dec_out[31:0] = 32'b00000000000000000000000000100000;
6'b1_00110 : dec_out[31:0] = 32'b00000000000000000000000001000000;
6'b1_00111 : dec_out[31:0] = 32'b00000000000000000000000010000000;
6'b1_01000 : dec_out[31:0] = 32'b00000000000000000000000100000000;
6'b1_01001 : dec_out[31:0] = 32'b00000000000000000000001000000000;
6'b1_01010 : dec_out[31:0] = 32'b00000000000000000000010000000000;
6'b1_01011 : dec_out[31:0] = 32'b00000000000000000000100000000000;
6'b1_01100 : dec_out[31:0] = 32'b00000000000000000001000000000000;
6'b1_01101 : dec_out[31:0] = 32'b00000000000000000010000000000000;
6'b1_01110 : dec_out[31:0] = 32'b00000000000000000100000000000000;
6'b1_01111 : dec_out[31:0] = 32'b00000000000000001000000000000000;
6'b1_10000 : dec_out[31:0] = 32'b00000000000000010000000000000000;
6'b1_10001 : dec_out[31:0] = 32'b00000000000000100000000000000000;
6'b1_10010 : dec_out[31:0] = 32'b00000000000001000000000000000000;
6'b1_10011 : dec_out[31:0] = 32'b00000000000010000000000000000000;
6'b1_10100 : dec_out[31:0] = 32'b00000000000100000000000000000000;
6'b1_10101 : dec_out[31:0] = 32'b00000000001000000000000000000000;
6'b1_10110 : dec_out[31:0] = 32'b00000000010000000000000000000000;
6'b1_10111 : dec_out[31:0] = 32'b00000000100000000000000000000000;
6'b1_11000 : dec_out[31:0] = 32'b00000001000000000000000000000000;
6'b1_11001 : dec_out[31:0] = 32'b00000010000000000000000000000000;
6'b1_11010 : dec_out[31:0] = 32'b00000100000000000000000000000000;
6'b1_11011 : dec_out[31:0] = 32'b00001000000000000000000000000000;
6'b1_11100 : dec_out[31:0] = 32'b00010000000000000000000000000000;
6'b1_11101 : dec_out[31:0] = 32'b00100000000000000000000000000000;
6'b1_11110 : dec_out[31:0] = 32'b01000000000000000000000000000000;
6'b1_11111 : dec_out[31:0] = 32'b10000000000000000000000000000000;
default : dec_out[31:0] = 32'b00000000000000000000000000000000;
endcase // casez ({enc_val,enc_in[4:0]})
end // always @ (*)
endmodule // oh_decoder5

4
common/hdl/oh_fifo_async.v
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@ -51,7 +51,7 @@ if(TYPE=="BASIC") begin : basic
fifo_model (
// Outputs
.full (full),
.prog_full (prog_full),
.prog_full (fifo_prog_full),
.dout (dout[DW-1:0]),
.empty (empty),
.valid (valid),
@ -69,7 +69,7 @@ else if (TYPE=="XILINX") begin : xilinx
fifo_async_104x32 fifo (
// Outputs
.full (full),
.prog_full (prog_full),
.prog_full (fifo_prog_full),
.dout (dout[DW-1:0]),
.empty (empty),
.valid (valid),

12
memory/hdl/fifo_cdc.v → common/hdl/oh_fifo_cdc.v
View File

@ -4,7 +4,7 @@
########################################################################
*/
module fifo_cdc (/*AUTOARG*/
module oh_fifo_cdc (/*AUTOARG*/
// Outputs
wait_out, access_out, packet_out,
// Inputs
@ -47,11 +47,13 @@ module fifo_cdc (/*AUTOARG*/
//We use the prog_full clean out any buffers in pipe that are too hard
//to stop. "slack"
assign wr_en = access_in;//
//Assumption: The "full" state should never be reached!
assign wr_en = access_in;
assign rd_en = ~empty & ~wait_in;
assign wait_out = prog_full;
//Keep access high until "acknowledge"
//Holds access high until "acknowledge"
always @ (posedge clk_out or negedge nreset)
if(!nreset)
access_out <=1'b0;
@ -61,9 +63,9 @@ module fifo_cdc (/*AUTOARG*/
//Read response fifo (from master)
defparam fifo.DW = DW;
defparam fifo.DEPTH = DEPTH;
defparam fifo.WAIT = WAIT;
defparam fifo.WAIT = WAIT;
fifo_async fifo (.prog_full (prog_full),//stay safe for now
oh_fifo_async fifo (.prog_full (prog_full),//stay safe for now
.full (full),
.rst (~nreset),
// Outputs

0
memory/hdl/fifo_sync.v → common/hdl/oh_fifo_sync.v
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2
elink/hdl/elink.v
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@ -241,7 +241,7 @@ module elink (/*AUTOARG*/
defparam ecfg_cdc.DW=104;
defparam ecfg_cdc.DEPTH=32;
fifo_cdc ecfg_cdc (.nreset (erx_nreset),
oh_fifo_cdc ecfg_cdc (.nreset (erx_nreset),
// Outputs
.wait_out (etx_cfg_wait),
.access_out (erx_cfg_access),

6
elink/hdl/erx_fifo.v
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@ -76,7 +76,7 @@ module erx_fifo (/*AUTOARG*/
//Read request fifo (from Epiphany)
fifo_cdc #(.DW(104), .DEPTH(32))
oh_fifo_cdc #(.DW(104), .DEPTH(32))
rxrd_fifo (
/*AUTOINST*/
// Outputs
@ -94,7 +94,7 @@ module erx_fifo (/*AUTOARG*/
//Write fifo (from Epiphany)
fifo_cdc #(.DW(104), .DEPTH(32))
oh_fifo_cdc #(.DW(104), .DEPTH(32))
rxwr_fifo(
/*AUTOINST*/
// Outputs
@ -111,7 +111,7 @@ module erx_fifo (/*AUTOARG*/
//Read response fifo (for host)
fifo_cdc #(.DW(104), .DEPTH(32))
oh_fifo_cdc #(.DW(104), .DEPTH(32))
rxrr_fifo(
/*AUTOINST*/
// Outputs

75
elink/hdl/erx_timer.v
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@ -1,75 +0,0 @@
module erx_timer (/*AUTOARG*/
// Outputs
timeout,
// Inputs
clk, reset, timer_cfg, stop_count, start_count
);
parameter DW = 32;
parameter AW = 32;
input clk;
input reset;
input [1:0] timer_cfg; //masks MSB of each byte (all zero is off)
input stop_count;
input start_count;
output timeout;
reg [31:0] timeout_reg;
reg do_count;
wire timer_en;
wire start_count_sync;
//Synchronize the start count
synchronizer #(.DW(1)) sync(
// Outputs
.out (start_count_sync),
// Inputs
.in (start_count),
.clk (clk),
.reset (reset)
);
assign timer_en = |(timer_cfg[1:0]);
always @ (posedge clk)
if(reset)
begin
do_count <=1'b0;
timeout_reg[31:0] <= 32'hffffffff;
end
else if(start_count_sync & timer_en)
begin
do_count <=1'b1;
timeout_reg[31:0] <= (timer_cfg[1:0]==2'b01) ? 32'h000000ff :
(timer_cfg[1:0]==2'b10) ? 32'h0000ffff :
32'hffffffff;
end
else if(stop_count)
begin
do_count <=1'b0;
end
else if(timer_expired)
begin
do_count <=1'b0;
timeout_reg[31:0] <= 32'hffffffff;
end
else if(do_count)
begin
timeout_reg[31:0] <= timeout_reg[31:0]-1'b1;
end
assign timer_expired = ~(|timeout_reg[31:0]);
assign timeout = timer_en & timer_expired;
endmodule // erx_timeout
// Local Variables:
// verilog-library-directories:("." "../../common/hdl" )
// End:

6
elink/hdl/etx_fifo.v
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@ -77,7 +77,7 @@ module etx_fifo(/*AUTOARG*/
*/
//Write fifo (from slave)
fifo_cdc #(.DW(104), .DEPTH(32)) txwr_fifo(
oh_fifo_cdc #(.DW(104), .DEPTH(32)) txwr_fifo(
/*AUTOINST*/
// Outputs
.wait_out (txwr_wait), // Templated
@ -92,7 +92,7 @@ module etx_fifo(/*AUTOARG*/
.wait_in (txwr_fifo_wait)); // Templated
//Read request fifo (from slave)
fifo_cdc #(.DW(104), .DEPTH(32)) txrd_fifo(
oh_fifo_cdc #(.DW(104), .DEPTH(32)) txrd_fifo(
/*AUTOINST*/
// Outputs
.wait_out (txrd_wait), // Templated
@ -109,7 +109,7 @@ module etx_fifo(/*AUTOARG*/
//Read response fifo (from master)
fifo_cdc #(.DW(104), .DEPTH(32)) txrr_fifo(
oh_fifo_cdc #(.DW(104), .DEPTH(32)) txrr_fifo(
/*AUTOINST*/
// Outputs

2
emailbox/hdl/emailbox.v
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@ -124,7 +124,7 @@ module emailbox (/*AUTOARG*/
defparam fifo.DW = MW;
defparam fifo.DEPTH = DEPTH;
//TODO: fix the width and depth
fifo_async fifo(.rst (~nreset),
oh_fifo_async fifo(.rst (~nreset),
// Outputs
.dout (mailbox_data[MW-1:0]),
.empty (mailbox_empty),

8
parallella/fpga/parallella_base/system_params.tcl
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@ -9,15 +9,15 @@ set root "../../.."
set partname "xc7z020clg400-1"
set hdl_files [list \
$root/common/hdl \
$root/memory/hdl \
$root/parallella/hdl/parallella_base.v \
$root/parallella/hdl \
$root/common/hdl/ \
$root/emesh/hdl \
$root/emmu/hdl \
$root/axi/hdl \
$root/emailbox/hdl \
$root/edma/hdl \
$root/elink/hdl \
$root/parallella/hdl \
$root/parallella/hdl/parallella_base.v \
]
set ip_files [list \

9
parallella/hdl/parallella_base.v
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@ -1,12 +1,3 @@
/*
* This is the top level module for the parallella base design:
* -
*
*
*
*
*/
module parallella_base(/*AUTOARG*/
// Outputs
s_axi_wready, s_axi_rvalid, s_axi_rresp, s_axi_rlast, s_axi_rid,