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Added profull HACK to async_fifo

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-this module needs rework
-needs to have same capabilities as standard FPGA async fifos
-remove this later
This commit is contained in:
Andreas Olofsson 2015-04-17 15:49:58 -04:00
parent 9f2cbb64cb
commit 7bc3b662ab
3 changed files with 36 additions and 7 deletions
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6
memory/hdl/fifo_async.v
View File

@ -2,7 +2,7 @@
module fifo_async
(/*AUTOARG*/
// Outputs
rd_data, rd_fifo_empty, wr_fifo_full,
rd_data, rd_fifo_empty, wr_fifo_full, wr_fifo_progfull,
// Inputs
reset, wr_clk, rd_clk, wr_write, wr_data, rd_read
);
@ -27,6 +27,7 @@ module fifo_async
output [DW-1:0] rd_data;
output rd_fifo_empty;
output wr_fifo_full;
output wr_fifo_progfull;
//Wires
wire [DW/8-1:0] wr_en;
@ -67,7 +68,8 @@ module fifo_async
//Write State Machine
fifo_full_block #(.AW(AW)) fifo_full_block(
// Outputs
.wr_fifo_full (wr_fifo_full),
.wr_fifo_progfull (wr_fifo_progfull),
.wr_fifo_full (wr_fifo_full),
.wr_addr (wr_addr[AW-1:0]),
.wr_gray_pointer (wr_gray_pointer[AW:0]),
// Inputs

12
memory/hdl/fifo_async_emesh.v
View File

@ -83,10 +83,16 @@ module fifo_async_emesh (/*AUTOARG*/
);
`elsif TARGET_CLEAN
wire tmp_progfull;
assign fifo_progfull = tmp_progfull | fifo_full;//HACK, need to fix this
fifo_async #(.DW(104), .AW(5)) fifo_async (
.rd_data (fifo_dout[103:0]),
.wr_fifo_full (fifo_progfull),
.rd_fifo_empty (fifo_empty),
.rd_data (fifo_dout[103:0]),
.wr_fifo_progfull (tmp_progfull),
.wr_fifo_full (fifo_full),
.rd_fifo_empty (fifo_empty),
//inputs
.reset (reset),
.wr_clk (wr_clk),

25
memory/hdl/fifo_full_block.v
View File

@ -18,7 +18,7 @@
*/
module fifo_full_block (/*AUTOARG*/
// Outputs
wr_fifo_full, wr_addr, wr_gray_pointer,
wr_fifo_full, wr_fifo_progfull, wr_addr, wr_gray_pointer,
// Inputs
reset, wr_clk, wr_rd_gray_pointer, wr_write
);
@ -38,6 +38,9 @@ module fifo_full_block (/*AUTOARG*/
//# OUTPUTS
//###########
output wr_fifo_full;
output wr_fifo_progfull;//TODO: hack!, fix this properly
//also make, programmable
output [AW-1:0] wr_addr;
output [AW:0] wr_gray_pointer;//for read domain
@ -55,6 +58,9 @@ module fifo_full_block (/*AUTOARG*/
wire [AW:0] wr_gray_next;
wire [AW:0] wr_binary_next;
wire wr_fifo_progfull_next;
reg wr_fifo_progfull;
//Counter States
always @(posedge wr_clk or posedge reset)
if(reset)
@ -85,6 +91,15 @@ module fifo_full_block (/*AUTOARG*/
(wr_gray_next[AW] ^ wr_rd_gray_pointer[AW]) &
(wr_gray_next[AW-1] ^ wr_rd_gray_pointer[AW-1]);
//FIFO almost full
assign wr_fifo_progfull_next =
(wr_gray_next[AW-3:0] == wr_rd_gray_pointer[AW-3:0]) &
(wr_gray_next[AW] ^ wr_rd_gray_pointer[AW]) &
(wr_gray_next[AW-1] ^ wr_rd_gray_pointer[AW-1]) &
(wr_gray_next[AW-2] ^ wr_rd_gray_pointer[AW-2]);
always @ (posedge wr_clk or posedge reset)
if(reset)
wr_fifo_full <= 1'b0;
@ -92,7 +107,13 @@ module fifo_full_block (/*AUTOARG*/
wr_fifo_full <=wr_fifo_full_next;
always @ (posedge wr_clk or posedge reset)
if(reset)
wr_fifo_progfull <= 1'b0;
else
wr_fifo_progfull <=wr_fifo_progfull_next;
endmodule // fifo_full_block