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MILESTONE: Yet another major revision of emesh protocol
-Remove formats and rally around 16bit CMD,simplicty over optimization! -Need to think of being scalable enough for 64bit memory and cache coherent systems!!!! The cost of this forward looking compatibility is only 8 bits, when compared to the 128 bits minimum of address/data pair, this is acceptable
This commit is contained in:
Andreas.Olofsson
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558776a3b3
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@ -7,22 +7,24 @@
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*
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* The following table shows the field mapping for different AW's:
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*
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* | Packet | AW16 | AW32 | AW64 | AW128 |
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* |---------|---------|----------|-----------|---------|
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* | 7:0 | CMDL | CMDL | CMDL | CMDL |
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* | 39:8 | D/SA,DA | DA0 | DA0 | DA0 |
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* | 71:40 | **** | D0/SA1(0)| D0/SA1 | D0/SA1 |
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* | 103:72 | **** | D1/SA0 | D1/SA0 | D1/SA0 |
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* | 135:104 | **** | ***,CMDH | DA1 | DA1 |
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* | 167:136 | **** | ***,CMDH | D2/CMDH | D2/SA2 |
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* | 199:168 | *** | **** | D3 | D3/SA3 |
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* | 231:200 | **** | ***,CMDH | ***,CMDH | DA2 |
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* | 263:232 | **** | **** | **** | DA3 |
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* | 295:264 | **** | ***,CMDH | ***,CMDH | D4/CMDH |
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* | 327:296 | **** | **** | **** | D5 |
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* | 359:328 | **** | **** | **** | D6 |
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* | 391:360 | **** | **** | **** | D7 |
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* | 399:392 | **** | ***,CMDH | ***,CMDH | CMDH |
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* | Packet | AW16 | AW32 | AW64 | AW128 |
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* |---------|---------|----------|--------|---------|
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* | 15:0 | DA,CMD | CMD | CMD | CMD |
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* | 47:16 | D/SA,DA | DA0 | DA0 | DA0 |
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* | 79:48 | **** | D0/SA0 | D0/SA0 | D0/SA0 |
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* | 111:80 | **** | D1/0 | D1/SA1 | D1/SA1 |
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* |---------|---------|----------|--------|---------|
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* | 143:112 | **** | *** | DA1 | DA1 |
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* |---------|---------|----------|--------|---------|
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* | 167:144 | **** | *** | D2 | D2/SA2 |
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* | 207:176 | *** | **** | D3 | D3/SA3 |
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* | 239:208 | **** | **** | **** | DA2 |
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* | 271:240 | **** | **** | **** | DA3 |
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* |---------|---------|----------|--------|---------|
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* | 303:272 | **** | **** | *** | D4 |
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* | 335:304 | **** | **** | **** | D5 |
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* | 367:336 | **** | **** | **** | D6 |
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* | 399:368 | **** | **** | **** | D7 |
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*
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* The following list shows the widths supported for each AW
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*
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@ -36,14 +38,14 @@
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*
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* | Command[15:0] | 15:8 | 7 | 6:4 | 3:0 |
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* |-----------------|-------|----------|-------------|-------|
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* | WRITE-SINGLE | CH | NEAR/FAR | SIZE[2:0] | 0000 |
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* | WRITE-IRQ | CH | NEAR/FAR | SIZE[2:0] | 0001 |
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* | WRITE-START | CH | NEAR/FAR | SIZE[2:0] | 0010 |
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* | WRITE-STREAM | CH | NEAR/FAR | SIZE[2:0] | 0011 |
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* | WRITE-STOP | CH | NEAR/FAR | SIZE[2:0] | 0100 |
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* | WRITE-MULTICAST | | NEAR/FAR | SIZE[2:0] | 0101 |
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* | WRITE-IO | CH | NEAR/FAR | 64,DIR[1:0] | 0110 |
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* | TBD | CH | NEAR/FAR | SIZE[2:0] | 0111 |
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* | WRITE-SINGLE | CTRL | NEAR/FAR | SIZE[2:0] | 0000 |
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* | WRITE-IRQ | CTRL | NEAR/FAR | SIZE[2:0] | 0001 |
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* | WRITE-START | LEN | NEAR/FAR | SIZE[2:0] | 0010 |
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* | WRITE-STREAM | CTRL | STOP | CTRL | 0011 |
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* | WRITE-MULTICAST | | NEAR/FAR | SIZE[2:0] | 0100 |
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* | WRITE-IO | | NEAR/FAR | 64,DIR[1:0] | 0101 |
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* | TBD | | NEAR/FAR | SIZE[2:0] | 0110 |
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* | TBD | | NEAR/FAR | SIZE[2:0] | 0111 |
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* |-----------------|-------|----------|-------------|-------|
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* | READ | CH | NEAR/FAR | SIZE[2:0] | 1000 |
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* | ATOMIC-OP | CH | NEAR/FAR | SIZE[2:0] | 1001 |
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@ -89,20 +91,16 @@ module emesh2packet
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output [PW-1:0] packet_out
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);
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//######################
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// PACKET COMMANDS
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//######################
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assign packet_out[7:0] = cmd_out[7:0];
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//Selector for src/data field
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assign write = cmd_out[3];
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generate
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//######################
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// 16-Bit
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//######################
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//############################
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// 16-Bit ("lite/apb like")
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//############################
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if(AW==16) begin : aw16
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if(PW==40) begin : p40
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assign packet_out[7:0] = cmd_out[7:0];
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assign packet_out[23:8] = dstaddr_out[15:0];
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assign packet_out[39:24] = write ? data_out[15:0]:
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srcaddr_out[15:0];
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@ -116,29 +114,18 @@ module emesh2packet
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// 32-Bit
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//######################
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if(AW==32) begin : aw32
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if(PW==72) begin: p72
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assign packet_out[39:8] = dstaddr_out[31:0];
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assign packet_out[71:40] = write ? data_out[31:0] :
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if(PW==80) begin: p80
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assign packet_out[15:0] = cmd_out[15:0];
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assign packet_out[47:16] = dstaddr_out[31:0];
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assign packet_out[79:48] = write ? data_out[31:0] :
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srcaddr_out[31:0];
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end
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else if(PW==80) begin: p80
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assign packet_out[39:8] = dstaddr_out[31:0];
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assign packet_out[71:40] = write ? data_out[31:0] :
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srcaddr_out[31:0];
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assign packet_out[79:72] = cmd_out[15:8];
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end
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else if(PW==104) begin: p104
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assign packet_out[39:8] = dstaddr_out[31:0];
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assign packet_out[71:40] = data_out[31:0];
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assign packet_out[103:72] = write ? data_out[63:32] :
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srcaddr_out[31:0];
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end
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else if(PW==112) begin: p112
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assign packet_out[39:8] = dstaddr_out[31:0];
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assign packet_out[71:40] = data_out[31:0];
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assign packet_out[103:72] = write ? data_out[63:32] :
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assign packet_out[15:0] = cmd_out[15:0];
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assign packet_out[47:16] = dstaddr_out[31:0];
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assign packet_out[79:48] = write ? data_out[31:0] :
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srcaddr_out[31:0];
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assign packet_out[111:104] = cmd_out[15:8];
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assign packet_out[111:80] = data_out[63:32];
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end
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else begin: perror
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initial
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@ -149,41 +136,20 @@ module emesh2packet
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// 64-Bit
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//######################
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if(AW==64) begin : aw64
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if(PW==136) begin: p136
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assign packet_out[39:8] = dstaddr_out[31:0];
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assign packet_out[71:40] = write ? data_out[31:0] :
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srcaddr_out[63:32];
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assign packet_out[103:72] = write ? data_out[63:32] :
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srcaddr_out[31:0];
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assign packet_out[135:104] = dstaddr_out[63:32];
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end
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else if(PW==144) begin: p144
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assign packet_out[39:8] = dstaddr_out[31:0];
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assign packet_out[71:40] = write ? data_out[31:0] :
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srcaddr_out[63:32];
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assign packet_out[103:72] = write ? data_out[63:32] :
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srcaddr_out[31:0];
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assign packet_out[135:104] = dstaddr_out[63:32];
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assign packet_out[143:136] = cmd_out[15:8];
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end
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else if(PW==200) begin: p200
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assign packet_out[39:8] = dstaddr_out[31:0];
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assign packet_out[71:40] = write ? data_out[31:0] :
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srcaddr_out[63:32];
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assign packet_out[103:72] = write ? data_out[63:32] :
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srcaddr_out[31:0];
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assign packet_out[135:104] = dstaddr_out[63:32];
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assign packet_out[199:136] = data_out[127:64];
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if(PW==144) begin: p144
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assign packet_out[15:0] = cmd_out[15:0];
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assign packet_out[47:16] = dstaddr_out[31:0];
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assign packet_out[111:48] = write ? data_out[63:0] :
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srcaddr_out[63:0];
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assign packet_out[143:112] = dstaddr_out[63:32];
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end
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else if(PW==208) begin: p208
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assign packet_out[39:8] = dstaddr_out[31:0];
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assign packet_out[71:40] = write ? data_out[31:0] :
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srcaddr_out[63:32];
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assign packet_out[103:72] = write ? data_out[63:32] :
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srcaddr_out[31:0];
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assign packet_out[135:104] = dstaddr_out[63:32];
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assign packet_out[199:136] = data_out[127:64];
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assign packet_out[207:200] = cmd_out[15:8];
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assign packet_out[15:0] = cmd_out[15:0];
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assign packet_out[47:16] = dstaddr_out[31:0];
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assign packet_out[111:48] = write ? data_out[63:0] :
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srcaddr_out[63:0];
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assign packet_out[143:112] = dstaddr_out[63:32];
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assign packet_out[207:144] = data_out[127:64];
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end
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else begin: perror
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initial
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@ -194,49 +160,26 @@ module emesh2packet
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// 128-Bit
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//######################
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if(AW==128) begin : aw128
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if(PW==264) begin: p264
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assign packet_out[39:8] = dstaddr_out[31:0];
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assign packet_out[71:40] = write ? data_out[31:0] :
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srcaddr_out[63:32];
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assign packet_out[103:72] = write ? data_out[63:32] :
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srcaddr_out[31:0];
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assign packet_out[135:104] = dstaddr_out[63:32];
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assign packet_out[199:136] = write ? data_out[127:64] :
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if(PW==272) begin: p272
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assign packet_out[15:0] = cmd_out[15:0];
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assign packet_out[47:16] = dstaddr_out[31:0];
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assign packet_out[111:48] = write ? data_out[63:0] :
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srcaddr_out[63:0];
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assign packet_out[143:112] = dstaddr_out[63:32];
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assign packet_out[207:144] = write ? data_out[127:64] :
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srcaddr_out[127:64];
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assign packet_out[263:200] = dstaddr_out[127:64];
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end
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else if(PW==272) begin: p272
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assign packet_out[39:8] = dstaddr_out[31:0];
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assign packet_out[71:40] = write ? data_out[31:0] :
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srcaddr_out[63:32];
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assign packet_out[103:72] = write ? data_out[63:32] :
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srcaddr_out[31:0];
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assign packet_out[135:104] = dstaddr_out[63:32];
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assign packet_out[199:136] = write ? data_out[127:64] :
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srcaddr_out[127:64];
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assign packet_out[271:264] = cmd_out[15:8];
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end
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else if(PW==392) begin: p392
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assign packet_out[39:8] = dstaddr_out[31:0];
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assign packet_out[71:40] = write ? data_out[31:0] :
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srcaddr_out[63:32];
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assign packet_out[103:72] = write ? data_out[63:32] :
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srcaddr_out[31:0];
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assign packet_out[135:104] = dstaddr_out[63:32];
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assign packet_out[199:136] = write ? data_out[127:64] :
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srcaddr_out[127:64];
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assign packet_out[391:264] = data_out[255:128];
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assign packet_out[271:208] = dstaddr_out[127:64];
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end
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else if(PW==400) begin: p400
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assign packet_out[39:8] = dstaddr_out[31:0];
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assign packet_out[71:40] = write ? data_out[31:0] :
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srcaddr_out[63:32];
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assign packet_out[103:72] = write ? data_out[63:32] :
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srcaddr_out[31:0];
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assign packet_out[135:104] = dstaddr_out[63:32];
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assign packet_out[199:136] = write ? data_out[127:64] :
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assign packet_out[15:0] = cmd_out[15:0];
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assign packet_out[47:16] = dstaddr_out[31:0];
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assign packet_out[111:48] = write ? data_out[63:0] :
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srcaddr_out[63:0];
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assign packet_out[143:112] = dstaddr_out[63:32];
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assign packet_out[207:144] = write ? data_out[127:64] :
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srcaddr_out[127:64];
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assign packet_out[399:392] = cmd_out[15:8];
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assign packet_out[271:208] = dstaddr_out[127:64];
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assign packet_out[399:272] = data_out[255:128];
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end
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else begin: perror
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initial
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