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Adding back awid, arid, lock to AXI interface
This commit is contained in:
Andreas Olofsson
parent
44a4d0e669
commit
7c93c565e9
@ -11,6 +11,7 @@ module dv_elink(/*AUTOARG*/
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parameter AW=32;
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parameter DW=32;
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parameter CW=2; //number of clocks to send int
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parameter IDW=12;
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//Basic
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input [CW-1:0] clk; // Core clock
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@ -51,7 +52,9 @@ module dv_elink(/*AUTOARG*/
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wire [31:0] dv_axi_araddr; // From emaxi of emaxi.v
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wire [1:0] dv_axi_arburst; // From emaxi of emaxi.v
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wire [3:0] dv_axi_arcache; // From emaxi of emaxi.v
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wire [IDW-1:0] dv_axi_arid; // From emaxi of emaxi.v
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wire [7:0] dv_axi_arlen; // From emaxi of emaxi.v
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wire [1:0] dv_axi_arlock; // From emaxi of emaxi.v
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wire [2:0] dv_axi_arprot; // From emaxi of emaxi.v
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wire [3:0] dv_axi_arqos; // From emaxi of emaxi.v
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wire dv_axi_arready; // From elink of elink.v
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@ -60,20 +63,25 @@ module dv_elink(/*AUTOARG*/
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wire [31:0] dv_axi_awaddr; // From emaxi of emaxi.v
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wire [1:0] dv_axi_awburst; // From emaxi of emaxi.v
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wire [3:0] dv_axi_awcache; // From emaxi of emaxi.v
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wire [IDW-1:0] dv_axi_awid; // From emaxi of emaxi.v
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wire [7:0] dv_axi_awlen; // From emaxi of emaxi.v
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wire [1:0] dv_axi_awlock; // From emaxi of emaxi.v
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wire [2:0] dv_axi_awprot; // From emaxi of emaxi.v
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wire [3:0] dv_axi_awqos; // From emaxi of emaxi.v
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wire dv_axi_awready; // From elink of elink.v
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wire [2:0] dv_axi_awsize; // From emaxi of emaxi.v
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wire dv_axi_awvalid; // From emaxi of emaxi.v
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wire [IDW-1:0] dv_axi_bid; // From elink of elink.v
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wire dv_axi_bready; // From emaxi of emaxi.v
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wire [1:0] dv_axi_bresp; // From elink of elink.v
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wire dv_axi_bvalid; // From elink of elink.v
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wire [IDW-1:0] dv_axi_rid; // From elink of elink.v
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wire dv_axi_rlast; // From elink of elink.v
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wire dv_axi_rready; // From emaxi of emaxi.v
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wire [1:0] dv_axi_rresp; // From elink of elink.v
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wire dv_axi_rvalid; // From elink of elink.v
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wire [63:0] dv_axi_wdata; // From emaxi of emaxi.v
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wire [IDW-1:0] dv_axi_wid; // From emaxi of emaxi.v
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wire dv_axi_wlast; // From emaxi of emaxi.v
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wire dv_axi_wready; // From elink of elink.v
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wire [7:0] dv_axi_wstrb; // From emaxi of emaxi.v
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@ -81,7 +89,9 @@ module dv_elink(/*AUTOARG*/
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wire [31:0] elink_axi_araddr; // From elink of elink.v
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wire [1:0] elink_axi_arburst; // From elink of elink.v
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wire [3:0] elink_axi_arcache; // From elink of elink.v
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wire [IDW-1:0] elink_axi_arid; // From elink of elink.v
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wire [7:0] elink_axi_arlen; // From elink of elink.v
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wire [1:0] elink_axi_arlock; // From elink of elink.v
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wire [2:0] elink_axi_arprot; // From elink of elink.v
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wire [3:0] elink_axi_arqos; // From elink of elink.v
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wire elink_axi_arready; // From esaxi of esaxi.v
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@ -90,21 +100,26 @@ module dv_elink(/*AUTOARG*/
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wire [31:0] elink_axi_awaddr; // From elink of elink.v
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wire [1:0] elink_axi_awburst; // From elink of elink.v
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wire [3:0] elink_axi_awcache; // From elink of elink.v
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wire [IDW-1:0] elink_axi_awid; // From elink of elink.v
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wire [7:0] elink_axi_awlen; // From elink of elink.v
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wire [1:0] elink_axi_awlock; // From elink of elink.v
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wire [2:0] elink_axi_awprot; // From elink of elink.v
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wire [3:0] elink_axi_awqos; // From elink of elink.v
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wire elink_axi_awready; // From esaxi of esaxi.v
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wire [2:0] elink_axi_awsize; // From elink of elink.v
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wire elink_axi_awvalid; // From elink of elink.v
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wire [IDW-1:0] elink_axi_bid; // From esaxi of esaxi.v
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wire elink_axi_bready; // From elink of elink.v
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wire [1:0] elink_axi_bresp; // From esaxi of esaxi.v
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wire elink_axi_bvalid; // From esaxi of esaxi.v
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wire [31:0] elink_axi_rdata; // From esaxi of esaxi.v
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wire [IDW-1:0] elink_axi_rid; // From esaxi of esaxi.v
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wire elink_axi_rlast; // From esaxi of esaxi.v
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wire elink_axi_rready; // From elink of elink.v
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wire [1:0] elink_axi_rresp; // From esaxi of esaxi.v
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wire elink_axi_rvalid; // From esaxi of esaxi.v
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wire [63:0] elink_axi_wdata; // From elink of elink.v
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wire [IDW-1:0] elink_axi_wid; // From elink of elink.v
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wire elink_axi_wlast; // From elink of elink.v
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wire elink_axi_wready; // From esaxi of esaxi.v
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wire [7:0] elink_axi_wstrb; // From elink of elink.v
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@ -261,23 +276,28 @@ module dv_elink(/*AUTOARG*/
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.emrr_srcaddr (emaxi_emrr_srcaddr[31:0]),
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/*AUTOINST*/
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// Outputs
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.m_axi_awid (dv_axi_awid[IDW-1:0]), // Templated
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.m_axi_awaddr (dv_axi_awaddr[31:0]), // Templated
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.m_axi_awlen (dv_axi_awlen[7:0]), // Templated
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.m_axi_awsize (dv_axi_awsize[2:0]), // Templated
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.m_axi_awburst (dv_axi_awburst[1:0]), // Templated
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.m_axi_awlock (dv_axi_awlock[1:0]), // Templated
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.m_axi_awcache (dv_axi_awcache[3:0]), // Templated
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.m_axi_awprot (dv_axi_awprot[2:0]), // Templated
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.m_axi_awqos (dv_axi_awqos[3:0]), // Templated
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.m_axi_awvalid (dv_axi_awvalid), // Templated
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.m_axi_wid (dv_axi_wid[IDW-1:0]), // Templated
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.m_axi_wdata (dv_axi_wdata[63:0]), // Templated
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.m_axi_wstrb (dv_axi_wstrb[7:0]), // Templated
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.m_axi_wlast (dv_axi_wlast), // Templated
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.m_axi_wvalid (dv_axi_wvalid), // Templated
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.m_axi_bready (dv_axi_bready), // Templated
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.m_axi_arid (dv_axi_arid[IDW-1:0]), // Templated
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.m_axi_araddr (dv_axi_araddr[31:0]), // Templated
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.m_axi_arlen (dv_axi_arlen[7:0]), // Templated
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.m_axi_arsize (dv_axi_arsize[2:0]), // Templated
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.m_axi_arburst (dv_axi_arburst[1:0]), // Templated
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.m_axi_arlock (dv_axi_arlock[1:0]), // Templated
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.m_axi_arcache (dv_axi_arcache[3:0]), // Templated
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.m_axi_arprot (dv_axi_arprot[2:0]), // Templated
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.m_axi_arqos (dv_axi_arqos[3:0]), // Templated
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@ -300,9 +320,11 @@ module dv_elink(/*AUTOARG*/
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.emrq_srcaddr (emaxi_emrq_srcaddr[31:0]), // Templated
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.m_axi_awready (dv_axi_awready), // Templated
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.m_axi_wready (dv_axi_wready), // Templated
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.m_axi_bid (dv_axi_bid[IDW-1:0]), // Templated
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.m_axi_bresp (dv_axi_bresp[1:0]), // Templated
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.m_axi_bvalid (dv_axi_bvalid), // Templated
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.m_axi_arready (dv_axi_arready), // Templated
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.m_axi_rid (dv_axi_rid[IDW-1:0]), // Templated
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.m_axi_rdata (dv_axi_rdata[63:0]), // Templated
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.m_axi_rresp (dv_axi_rresp[1:0]), // Templated
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.m_axi_rlast (dv_axi_rlast), // Templated
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@ -358,25 +380,31 @@ module dv_elink(/*AUTOARG*/
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.mi_din (), // Templated
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.s_axi_arready (elink_axi_arready), // Templated
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.s_axi_awready (elink_axi_awready), // Templated
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.s_axi_bid (elink_axi_bid[IDW-1:0]), // Templated
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.s_axi_bresp (elink_axi_bresp[1:0]), // Templated
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.s_axi_bvalid (elink_axi_bvalid), // Templated
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.s_axi_rid (elink_axi_rid[IDW-1:0]), // Templated
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.s_axi_rdata (elink_axi_rdata[31:0]), // Templated
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.s_axi_rlast (elink_axi_rlast), // Templated
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.s_axi_rresp (elink_axi_rresp[1:0]), // Templated
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.s_axi_rvalid (elink_axi_rvalid), // Templated
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.s_axi_wready (elink_axi_wready), // Templated
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// Inputs
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.s_axi_arid (elink_axi_arid[IDW-1:0]), // Templated
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.s_axi_araddr (elink_axi_araddr[31:0]), // Templated
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.s_axi_arburst (elink_axi_arburst[1:0]), // Templated
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.s_axi_arcache (elink_axi_arcache[3:0]), // Templated
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.s_axi_arlock (elink_axi_arlock[1:0]), // Templated
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.s_axi_arlen (elink_axi_arlen[7:0]), // Templated
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.s_axi_arprot (elink_axi_arprot[2:0]), // Templated
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.s_axi_arqos (elink_axi_arqos[3:0]), // Templated
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.s_axi_arsize (elink_axi_arsize[2:0]), // Templated
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.s_axi_arvalid (elink_axi_arvalid), // Templated
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.s_axi_awid (elink_axi_awid[IDW-1:0]), // Templated
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.s_axi_awaddr (elink_axi_awaddr[31:0]), // Templated
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.s_axi_awburst (elink_axi_awburst[1:0]), // Templated
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.s_axi_awcache (elink_axi_awcache[3:0]), // Templated
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.s_axi_awlock (elink_axi_awlock[1:0]), // Templated
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.s_axi_awlen (elink_axi_awlen[7:0]), // Templated
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.s_axi_awprot (elink_axi_awprot[2:0]), // Templated
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.s_axi_awqos (elink_axi_awqos[3:0]), // Templated
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@ -384,6 +412,7 @@ module dv_elink(/*AUTOARG*/
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.s_axi_awvalid (elink_axi_awvalid), // Templated
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.s_axi_bready (elink_axi_bready), // Templated
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.s_axi_rready (elink_axi_rready), // Templated
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.s_axi_wid (elink_axi_wid[IDW-1:0]), // Templated
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.s_axi_wdata (elink_axi_wdata[31:0]), // Templated
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.s_axi_wlast (elink_axi_wlast), // Templated
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.s_axi_wstrb (elink_axi_wstrb[3:0]), // Templated
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@ -430,32 +459,39 @@ module dv_elink(/*AUTOARG*/
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.txo_frame_n (frame_n), // Templated
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.txo_data_p (data_p[7:0]), // Templated
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.txo_data_n (data_n[7:0]), // Templated
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.m_axi_araddr (elink_axi_araddr[31:0]), // Templated
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.m_axi_arburst (elink_axi_arburst[1:0]), // Templated
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.m_axi_arcache (elink_axi_arcache[3:0]), // Templated
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.m_axi_arlen (elink_axi_arlen[7:0]), // Templated
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.m_axi_arprot (elink_axi_arprot[2:0]), // Templated
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.m_axi_arqos (elink_axi_arqos[3:0]), // Templated
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.m_axi_arsize (elink_axi_arsize[2:0]), // Templated
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.m_axi_arvalid (elink_axi_arvalid), // Templated
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.m_axi_awid (elink_axi_awid[IDW-1:0]), // Templated
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.m_axi_awaddr (elink_axi_awaddr[31:0]), // Templated
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.m_axi_awburst (elink_axi_awburst[1:0]), // Templated
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.m_axi_awcache (elink_axi_awcache[3:0]), // Templated
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.m_axi_awlen (elink_axi_awlen[7:0]), // Templated
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.m_axi_awsize (elink_axi_awsize[2:0]), // Templated
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.m_axi_awburst (elink_axi_awburst[1:0]), // Templated
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.m_axi_awlock (elink_axi_awlock[1:0]), // Templated
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.m_axi_awcache (elink_axi_awcache[3:0]), // Templated
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.m_axi_awprot (elink_axi_awprot[2:0]), // Templated
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.m_axi_awqos (elink_axi_awqos[3:0]), // Templated
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.m_axi_awsize (elink_axi_awsize[2:0]), // Templated
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.m_axi_awvalid (elink_axi_awvalid), // Templated
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.m_axi_bready (elink_axi_bready), // Templated
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.m_axi_rready (elink_axi_rready), // Templated
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.m_axi_wid (elink_axi_wid[IDW-1:0]), // Templated
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.m_axi_wdata (elink_axi_wdata[63:0]), // Templated
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.m_axi_wlast (elink_axi_wlast), // Templated
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.m_axi_wstrb (elink_axi_wstrb[7:0]), // Templated
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.m_axi_wlast (elink_axi_wlast), // Templated
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.m_axi_wvalid (elink_axi_wvalid), // Templated
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.m_axi_bready (elink_axi_bready), // Templated
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.m_axi_arid (elink_axi_arid[IDW-1:0]), // Templated
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.m_axi_araddr (elink_axi_araddr[31:0]), // Templated
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.m_axi_arlen (elink_axi_arlen[7:0]), // Templated
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.m_axi_arsize (elink_axi_arsize[2:0]), // Templated
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.m_axi_arburst (elink_axi_arburst[1:0]), // Templated
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.m_axi_arlock (elink_axi_arlock[1:0]), // Templated
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.m_axi_arcache (elink_axi_arcache[3:0]), // Templated
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.m_axi_arprot (elink_axi_arprot[2:0]), // Templated
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.m_axi_arqos (elink_axi_arqos[3:0]), // Templated
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.m_axi_arvalid (elink_axi_arvalid), // Templated
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.m_axi_rready (elink_axi_rready), // Templated
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.s_axi_arready (dv_axi_arready), // Templated
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.s_axi_awready (dv_axi_awready), // Templated
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.s_axi_bid (dv_axi_bid[IDW-1:0]), // Templated
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.s_axi_bresp (dv_axi_bresp[1:0]), // Templated
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.s_axi_bvalid (dv_axi_bvalid), // Templated
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.s_axi_rid (dv_axi_rid[IDW-1:0]), // Templated
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.s_axi_rdata (dv_axi_rdata[31:0]), // Templated
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.s_axi_rlast (dv_axi_rlast), // Templated
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.s_axi_rresp (dv_axi_rresp[1:0]), // Templated
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@ -472,26 +508,32 @@ module dv_elink(/*AUTOARG*/
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.txi_wr_wait_n (wr_wait_n), // Templated
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.txi_rd_wait_p (rd_wait_p), // Templated
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.txi_rd_wait_n (rd_wait_n), // Templated
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.m_axi_arready (elink_axi_arready), // Templated
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.m_axi_awready (elink_axi_awready), // Templated
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.m_axi_wready (elink_axi_wready), // Templated
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.m_axi_bid (elink_axi_bid[IDW-1:0]), // Templated
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.m_axi_bresp (elink_axi_bresp[1:0]), // Templated
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.m_axi_bvalid (elink_axi_bvalid), // Templated
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.m_axi_arready (elink_axi_arready), // Templated
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.m_axi_rid (elink_axi_rid[IDW-1:0]), // Templated
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.m_axi_rdata ({32'b0,elink_axi_rdata[31:0]}), // Templated
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.m_axi_rlast (elink_axi_rlast), // Templated
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.m_axi_rresp (elink_axi_rresp[1:0]), // Templated
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.m_axi_rlast (elink_axi_rlast), // Templated
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.m_axi_rvalid (elink_axi_rvalid), // Templated
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.m_axi_wready (elink_axi_wready), // Templated
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.s_axi_arid (dv_axi_arid[IDW-1:0]), // Templated
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.s_axi_araddr (dv_axi_araddr[31:0]), // Templated
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.s_axi_arburst (dv_axi_arburst[1:0]), // Templated
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.s_axi_arcache (dv_axi_arcache[3:0]), // Templated
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.s_axi_arlock (dv_axi_arlock[1:0]), // Templated
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.s_axi_arlen (dv_axi_arlen[7:0]), // Templated
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.s_axi_arprot (dv_axi_arprot[2:0]), // Templated
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.s_axi_arqos (dv_axi_arqos[3:0]), // Templated
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.s_axi_arsize (dv_axi_arsize[2:0]), // Templated
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.s_axi_arvalid (dv_axi_arvalid), // Templated
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.s_axi_awid (dv_axi_awid[IDW-1:0]), // Templated
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.s_axi_awaddr (dv_axi_awaddr[31:0]), // Templated
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.s_axi_awburst (dv_axi_awburst[1:0]), // Templated
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.s_axi_awcache (dv_axi_awcache[3:0]), // Templated
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.s_axi_awlock (dv_axi_awlock[1:0]), // Templated
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.s_axi_awlen (dv_axi_awlen[7:0]), // Templated
|
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.s_axi_awprot (dv_axi_awprot[2:0]), // Templated
|
||||
.s_axi_awqos (dv_axi_awqos[3:0]), // Templated
|
||||
@ -499,6 +541,7 @@ module dv_elink(/*AUTOARG*/
|
||||
.s_axi_awvalid (dv_axi_awvalid), // Templated
|
||||
.s_axi_bready (dv_axi_bready), // Templated
|
||||
.s_axi_rready (dv_axi_rready), // Templated
|
||||
.s_axi_wid (dv_axi_wid[IDW-1:0]), // Templated
|
||||
.s_axi_wdata (dv_axi_wdata[31:0]), // Templated
|
||||
.s_axi_wlast (dv_axi_wlast), // Templated
|
||||
.s_axi_wstrb (dv_axi_wstrb[3:0]), // Templated
|
||||
|
||||
@ -254,32 +254,34 @@ module elink(/*AUTOARG*/
|
||||
colid, rowid, chip_resetb, cclk_p, cclk_n, rxo_wr_wait_p,
|
||||
rxo_wr_wait_n, rxo_rd_wait_p, rxo_rd_wait_n, txo_lclk_p,
|
||||
txo_lclk_n, txo_frame_p, txo_frame_n, txo_data_p, txo_data_n,
|
||||
m_axi_araddr, m_axi_arburst, m_axi_arcache, m_axi_arlen,
|
||||
m_axi_arprot, m_axi_arqos, m_axi_arsize, m_axi_arvalid,
|
||||
m_axi_awaddr, m_axi_awburst, m_axi_awcache, m_axi_awlen,
|
||||
m_axi_awprot, m_axi_awqos, m_axi_awsize, m_axi_awvalid,
|
||||
m_axi_bready, m_axi_rready, m_axi_wdata, m_axi_wlast, m_axi_wstrb,
|
||||
m_axi_wvalid, s_axi_arready, s_axi_awready, s_axi_bresp,
|
||||
s_axi_bvalid, s_axi_rdata, s_axi_rlast, s_axi_rresp, s_axi_rvalid,
|
||||
m_axi_awid, m_axi_awaddr, m_axi_awlen, m_axi_awsize, m_axi_awburst,
|
||||
m_axi_awlock, m_axi_awcache, m_axi_awprot, m_axi_awqos,
|
||||
m_axi_awvalid, m_axi_wid, m_axi_wdata, m_axi_wstrb, m_axi_wlast,
|
||||
m_axi_wvalid, m_axi_bready, m_axi_arid, m_axi_araddr, m_axi_arlen,
|
||||
m_axi_arsize, m_axi_arburst, m_axi_arlock, m_axi_arcache,
|
||||
m_axi_arprot, m_axi_arqos, m_axi_arvalid, m_axi_rready,
|
||||
s_axi_arready, s_axi_awready, s_axi_bid, s_axi_bresp, s_axi_bvalid,
|
||||
s_axi_rid, s_axi_rdata, s_axi_rlast, s_axi_rresp, s_axi_rvalid,
|
||||
s_axi_wready, embox_not_empty, embox_full,
|
||||
// Inputs
|
||||
hard_reset, clkin, clkbypass, rxi_lclk_p, rxi_lclk_n, rxi_frame_p,
|
||||
rxi_frame_n, rxi_data_p, rxi_data_n, txi_wr_wait_p, txi_wr_wait_n,
|
||||
txi_rd_wait_p, txi_rd_wait_n, m_axi_aclk, m_axi_aresetn,
|
||||
m_axi_arready, m_axi_awready, m_axi_bresp, m_axi_bvalid,
|
||||
m_axi_rdata, m_axi_rlast, m_axi_rresp, m_axi_rvalid, m_axi_wready,
|
||||
s_axi_aclk, s_axi_aresetn, s_axi_araddr, s_axi_arburst,
|
||||
s_axi_arcache, s_axi_arlen, s_axi_arprot, s_axi_arqos,
|
||||
s_axi_arsize, s_axi_arvalid, s_axi_awaddr, s_axi_awburst,
|
||||
s_axi_awcache, s_axi_awlen, s_axi_awprot, s_axi_awqos,
|
||||
s_axi_awsize, s_axi_awvalid, s_axi_bready, s_axi_rready,
|
||||
s_axi_wdata, s_axi_wlast, s_axi_wstrb, s_axi_wvalid
|
||||
m_axi_awready, m_axi_wready, m_axi_bid, m_axi_bresp, m_axi_bvalid,
|
||||
m_axi_arready, m_axi_rid, m_axi_rdata, m_axi_rresp, m_axi_rlast,
|
||||
m_axi_rvalid, s_axi_aclk, s_axi_aresetn, s_axi_arid, s_axi_araddr,
|
||||
s_axi_arburst, s_axi_arcache, s_axi_arlock, s_axi_arlen,
|
||||
s_axi_arprot, s_axi_arqos, s_axi_arsize, s_axi_arvalid, s_axi_awid,
|
||||
s_axi_awaddr, s_axi_awburst, s_axi_awcache, s_axi_awlock,
|
||||
s_axi_awlen, s_axi_awprot, s_axi_awqos, s_axi_awsize,
|
||||
s_axi_awvalid, s_axi_bready, s_axi_rready, s_axi_wid, s_axi_wdata,
|
||||
s_axi_wlast, s_axi_wstrb, s_axi_wvalid
|
||||
);
|
||||
|
||||
parameter DEF_COREID = 12'h810;
|
||||
parameter AW = 32;
|
||||
parameter DW = 32;
|
||||
parameter IDW = 32;
|
||||
parameter IDW = 12;
|
||||
parameter RFAW = 13;
|
||||
parameter MW = 44;
|
||||
parameter INC_PLL = 1; //include pll
|
||||
@ -322,98 +324,112 @@ module elink(/*AUTOARG*/
|
||||
/*AXI master interface */
|
||||
/*****************************/
|
||||
//Clock and reset
|
||||
input m_axi_aclk; //axi master clock
|
||||
input m_axi_aresetn; //axi master reset (active low)
|
||||
|
||||
//Read address channel
|
||||
output [31:0] m_axi_araddr; //read address
|
||||
output [1:0] m_axi_arburst; //burst type
|
||||
output [3:0] m_axi_arcache; //memory type
|
||||
output [7:0] m_axi_arlen; //burst length (number of data transfers)
|
||||
output [2:0] m_axi_arprot; //protection type
|
||||
output [3:0] m_axi_arqos; //quality of service (setting?)
|
||||
input m_axi_arready; //read ready
|
||||
output [2:0] m_axi_arsize; //burst size (the size of each transfer)
|
||||
output m_axi_arvalid; //write address valid
|
||||
input m_axi_aclk; //axi master clock
|
||||
input m_axi_aresetn; //axi master reset (active low)
|
||||
|
||||
//Write address channel
|
||||
output [31:0] m_axi_awaddr;
|
||||
output [1:0] m_axi_awburst;
|
||||
output [3:0] m_axi_awcache;
|
||||
output [7:0] m_axi_awlen;
|
||||
output [2:0] m_axi_awprot;
|
||||
output [3:0] m_axi_awqos;
|
||||
input m_axi_awready;
|
||||
output [2:0] m_axi_awsize;
|
||||
output m_axi_awvalid;
|
||||
|
||||
//Write response channel
|
||||
output m_axi_bready;
|
||||
input [1:0] m_axi_bresp;
|
||||
input m_axi_bvalid;
|
||||
|
||||
//Read data channel
|
||||
input [63:0] m_axi_rdata;
|
||||
input m_axi_rlast; //indicates last transfer of a burst
|
||||
output m_axi_rready; //read ready signal
|
||||
input [1:0] m_axi_rresp;
|
||||
input m_axi_rvalid;
|
||||
|
||||
output [IDW-1:0] m_axi_awid; // write address ID
|
||||
output [31 : 0] m_axi_awaddr; // master interface write address
|
||||
output [7 : 0] m_axi_awlen; // burst length.
|
||||
output [2 : 0] m_axi_awsize; // burst size.
|
||||
output [1 : 0] m_axi_awburst; // burst type.
|
||||
output [1:0] m_axi_awlock; // lock type
|
||||
output [3 : 0] m_axi_awcache; // memory type.
|
||||
output [2 : 0] m_axi_awprot; // protection type.
|
||||
output [3 : 0] m_axi_awqos; // quality of service
|
||||
output m_axi_awvalid; // write address valid
|
||||
input m_axi_awready; // write address ready
|
||||
|
||||
//Write data channel
|
||||
output [63:0] m_axi_wdata;
|
||||
output m_axi_wlast; //indicates last transfer of a burs
|
||||
input m_axi_wready; //response ready
|
||||
output [7:0] m_axi_wstrb;
|
||||
output m_axi_wvalid;
|
||||
output [IDW-1:0] m_axi_wid;
|
||||
output [63 : 0] m_axi_wdata; // master interface write data.
|
||||
output [7 : 0] m_axi_wstrb; // byte write strobes
|
||||
output m_axi_wlast; // indicates last transfer in a write burst.
|
||||
output m_axi_wvalid; // indicates data is ready to go
|
||||
input m_axi_wready; // indicates that the slave is ready for data
|
||||
|
||||
//Write response channel
|
||||
input [IDW-1:0] m_axi_bid;
|
||||
input [1 : 0] m_axi_bresp; // status of the write transaction.
|
||||
input m_axi_bvalid; // channel is signaling a valid write response
|
||||
output m_axi_bready; // master can accept write response.
|
||||
|
||||
//Read address channel
|
||||
output [IDW-1:0] m_axi_arid; // read address ID
|
||||
output [31 : 0] m_axi_araddr; // initial address of a read burst
|
||||
output [7 : 0] m_axi_arlen; // burst length
|
||||
output [2 : 0] m_axi_arsize; // burst size
|
||||
output [1 : 0] m_axi_arburst; // burst type
|
||||
output [1 : 0] m_axi_arlock; //lock type
|
||||
output [3 : 0] m_axi_arcache; // memory type
|
||||
output [2 : 0] m_axi_arprot; // protection type
|
||||
output [3 : 0] m_axi_arqos; //
|
||||
output m_axi_arvalid; // valid read address and control information
|
||||
input m_axi_arready; // slave is ready to accept an address
|
||||
|
||||
//Read data channel
|
||||
input [IDW-1:0] m_axi_rid;
|
||||
input [63 : 0] m_axi_rdata; // master read data
|
||||
input [1 : 0] m_axi_rresp; // status of the read transfer
|
||||
input m_axi_rlast; // signals last transfer in a read burst
|
||||
input m_axi_rvalid; // signaling the required read data
|
||||
output m_axi_rready; // master can accept the readback data
|
||||
|
||||
/*****************************/
|
||||
/*AXI slave interface */
|
||||
/*****************************/
|
||||
//Clock and reset
|
||||
input s_axi_aclk;
|
||||
input s_axi_aresetn;
|
||||
input s_axi_aclk;
|
||||
input s_axi_aresetn;
|
||||
|
||||
//Read address channel
|
||||
input [31:0] s_axi_araddr;
|
||||
input [1:0] s_axi_arburst;
|
||||
input [3:0] s_axi_arcache;
|
||||
input [7:0] s_axi_arlen;
|
||||
input [2:0] s_axi_arprot;
|
||||
input [3:0] s_axi_arqos;
|
||||
output s_axi_arready;
|
||||
input [2:0] s_axi_arsize;
|
||||
input s_axi_arvalid;
|
||||
input [IDW-1:0] s_axi_arid; //write address ID
|
||||
input [31:0] s_axi_araddr;
|
||||
input [1:0] s_axi_arburst;
|
||||
input [3:0] s_axi_arcache;
|
||||
input [1:0] s_axi_arlock;
|
||||
input [7:0] s_axi_arlen;
|
||||
input [2:0] s_axi_arprot;
|
||||
input [3:0] s_axi_arqos;
|
||||
output s_axi_arready;
|
||||
input [2:0] s_axi_arsize;
|
||||
input s_axi_arvalid;
|
||||
|
||||
//Write address channel
|
||||
input [31:0] s_axi_awaddr;
|
||||
input [1:0] s_axi_awburst;
|
||||
input [3:0] s_axi_awcache;
|
||||
input [7:0] s_axi_awlen;
|
||||
input [2:0] s_axi_awprot;
|
||||
input [3:0] s_axi_awqos;
|
||||
output s_axi_awready;
|
||||
input [2:0] s_axi_awsize;
|
||||
input s_axi_awvalid;
|
||||
input [IDW-1:0] s_axi_awid; //write address ID
|
||||
input [31:0] s_axi_awaddr;
|
||||
input [1:0] s_axi_awburst;
|
||||
input [3:0] s_axi_awcache;
|
||||
input [1:0] s_axi_awlock;
|
||||
input [7:0] s_axi_awlen;
|
||||
input [2:0] s_axi_awprot;
|
||||
input [3:0] s_axi_awqos;
|
||||
input [2:0] s_axi_awsize;
|
||||
input s_axi_awvalid;
|
||||
output s_axi_awready;
|
||||
|
||||
//Buffered write response channel
|
||||
input s_axi_bready;
|
||||
output [1:0] s_axi_bresp;
|
||||
output s_axi_bvalid;
|
||||
|
||||
//Read channel
|
||||
output [31:0] s_axi_rdata;
|
||||
output s_axi_rlast;
|
||||
input s_axi_rready;
|
||||
output [1:0] s_axi_rresp;
|
||||
output s_axi_rvalid;
|
||||
output [IDW-1:0] s_axi_bid; //write address ID
|
||||
output [1:0] s_axi_bresp;
|
||||
output s_axi_bvalid;
|
||||
input s_axi_bready;
|
||||
|
||||
//Write channel
|
||||
input [31:0] s_axi_wdata;
|
||||
input s_axi_wlast;
|
||||
output s_axi_wready;
|
||||
input [3:0] s_axi_wstrb;
|
||||
input s_axi_wvalid;
|
||||
//Read channel
|
||||
output [IDW-1:0] s_axi_rid; //write address ID
|
||||
output [31:0] s_axi_rdata;
|
||||
output s_axi_rlast;
|
||||
output [1:0] s_axi_rresp;
|
||||
output s_axi_rvalid;
|
||||
input s_axi_rready;
|
||||
|
||||
//Write channel
|
||||
input [IDW-1:0] s_axi_wid; //write address ID
|
||||
input [31:0] s_axi_wdata;
|
||||
input s_axi_wlast;
|
||||
input [3:0] s_axi_wstrb;
|
||||
input s_axi_wvalid;
|
||||
output s_axi_wready;
|
||||
|
||||
/*****************************/
|
||||
/*MAILBOX (interrupts) */
|
||||
/*****************************/
|
||||
@ -521,7 +537,8 @@ module elink(/*AUTOARG*/
|
||||
.em\(.*\) (emaxi_em\1[]),
|
||||
);
|
||||
*/
|
||||
|
||||
defparam emaxi.IDW =IDW; //ID width from instantiation
|
||||
|
||||
emaxi emaxi(
|
||||
/*AUTOINST*/
|
||||
// Outputs
|
||||
@ -534,23 +551,28 @@ module elink(/*AUTOARG*/
|
||||
.emrr_dstaddr (emaxi_emrr_dstaddr[31:0]), // Templated
|
||||
.emrr_data (emaxi_emrr_data[31:0]), // Templated
|
||||
.emrr_srcaddr (emaxi_emrr_srcaddr[31:0]), // Templated
|
||||
.m_axi_awid (m_axi_awid[IDW-1:0]),
|
||||
.m_axi_awaddr (m_axi_awaddr[31:0]),
|
||||
.m_axi_awlen (m_axi_awlen[7:0]),
|
||||
.m_axi_awsize (m_axi_awsize[2:0]),
|
||||
.m_axi_awburst (m_axi_awburst[1:0]),
|
||||
.m_axi_awlock (m_axi_awlock[1:0]),
|
||||
.m_axi_awcache (m_axi_awcache[3:0]),
|
||||
.m_axi_awprot (m_axi_awprot[2:0]),
|
||||
.m_axi_awqos (m_axi_awqos[3:0]),
|
||||
.m_axi_awvalid (m_axi_awvalid),
|
||||
.m_axi_wid (m_axi_wid[IDW-1:0]),
|
||||
.m_axi_wdata (m_axi_wdata[63:0]),
|
||||
.m_axi_wstrb (m_axi_wstrb[7:0]),
|
||||
.m_axi_wlast (m_axi_wlast),
|
||||
.m_axi_wvalid (m_axi_wvalid),
|
||||
.m_axi_bready (m_axi_bready),
|
||||
.m_axi_arid (m_axi_arid[IDW-1:0]),
|
||||
.m_axi_araddr (m_axi_araddr[31:0]),
|
||||
.m_axi_arlen (m_axi_arlen[7:0]),
|
||||
.m_axi_arsize (m_axi_arsize[2:0]),
|
||||
.m_axi_arburst (m_axi_arburst[1:0]),
|
||||
.m_axi_arlock (m_axi_arlock[1:0]),
|
||||
.m_axi_arcache (m_axi_arcache[3:0]),
|
||||
.m_axi_arprot (m_axi_arprot[2:0]),
|
||||
.m_axi_arqos (m_axi_arqos[3:0]),
|
||||
@ -576,9 +598,11 @@ module elink(/*AUTOARG*/
|
||||
.m_axi_aresetn (m_axi_aresetn),
|
||||
.m_axi_awready (m_axi_awready),
|
||||
.m_axi_wready (m_axi_wready),
|
||||
.m_axi_bid (m_axi_bid[IDW-1:0]),
|
||||
.m_axi_bresp (m_axi_bresp[1:0]),
|
||||
.m_axi_bvalid (m_axi_bvalid),
|
||||
.m_axi_arready (m_axi_arready),
|
||||
.m_axi_rid (m_axi_rid[IDW-1:0]),
|
||||
.m_axi_rdata (m_axi_rdata[63:0]),
|
||||
.m_axi_rresp (m_axi_rresp[1:0]),
|
||||
.m_axi_rlast (m_axi_rlast),
|
||||
@ -596,7 +620,9 @@ module elink(/*AUTOARG*/
|
||||
);
|
||||
*/
|
||||
|
||||
defparam esaxi.ELINKID=ELINKID; //passing along ID from top level
|
||||
defparam esaxi.ELINKID=ELINKID; //passing along ID from top level
|
||||
defparam esaxi.IDW =IDW; //ID width from instantiation
|
||||
|
||||
esaxi esaxi(
|
||||
/*AUTOINST*/
|
||||
// Outputs
|
||||
@ -625,8 +651,10 @@ module elink(/*AUTOARG*/
|
||||
.mi_din (mi_din[31:0]),
|
||||
.s_axi_arready (s_axi_arready),
|
||||
.s_axi_awready (s_axi_awready),
|
||||
.s_axi_bid (s_axi_bid[IDW-1:0]),
|
||||
.s_axi_bresp (s_axi_bresp[1:0]),
|
||||
.s_axi_bvalid (s_axi_bvalid),
|
||||
.s_axi_rid (s_axi_rid[IDW-1:0]),
|
||||
.s_axi_rdata (s_axi_rdata[31:0]),
|
||||
.s_axi_rlast (s_axi_rlast),
|
||||
.s_axi_rresp (s_axi_rresp[1:0]),
|
||||
@ -646,17 +674,21 @@ module elink(/*AUTOARG*/
|
||||
.ecfg_timeout_enable (ecfg_timeout_enable),
|
||||
.s_axi_aclk (s_axi_aclk),
|
||||
.s_axi_aresetn (s_axi_aresetn),
|
||||
.s_axi_arid (s_axi_arid[IDW-1:0]),
|
||||
.s_axi_araddr (s_axi_araddr[31:0]),
|
||||
.s_axi_arburst (s_axi_arburst[1:0]),
|
||||
.s_axi_arcache (s_axi_arcache[3:0]),
|
||||
.s_axi_arlock (s_axi_arlock[1:0]),
|
||||
.s_axi_arlen (s_axi_arlen[7:0]),
|
||||
.s_axi_arprot (s_axi_arprot[2:0]),
|
||||
.s_axi_arqos (s_axi_arqos[3:0]),
|
||||
.s_axi_arsize (s_axi_arsize[2:0]),
|
||||
.s_axi_arvalid (s_axi_arvalid),
|
||||
.s_axi_awid (s_axi_awid[IDW-1:0]),
|
||||
.s_axi_awaddr (s_axi_awaddr[31:0]),
|
||||
.s_axi_awburst (s_axi_awburst[1:0]),
|
||||
.s_axi_awcache (s_axi_awcache[3:0]),
|
||||
.s_axi_awlock (s_axi_awlock[1:0]),
|
||||
.s_axi_awlen (s_axi_awlen[7:0]),
|
||||
.s_axi_awprot (s_axi_awprot[2:0]),
|
||||
.s_axi_awqos (s_axi_awqos[3:0]),
|
||||
@ -664,6 +696,7 @@ module elink(/*AUTOARG*/
|
||||
.s_axi_awvalid (s_axi_awvalid),
|
||||
.s_axi_bready (s_axi_bready),
|
||||
.s_axi_rready (s_axi_rready),
|
||||
.s_axi_wid (s_axi_wid[IDW-1:0]),
|
||||
.s_axi_wdata (s_axi_wdata[31:0]),
|
||||
.s_axi_wlast (s_axi_wlast),
|
||||
.s_axi_wstrb (s_axi_wstrb[3:0]),
|
||||
|
||||
@ -1,28 +1,30 @@
|
||||
/*
|
||||
########################################################################
|
||||
Epiphany eLink AXI Master Module
|
||||
########################################################################
|
||||
|
||||
########################################################################
|
||||
*/
|
||||
|
||||
module emaxi(/*autoarg*/
|
||||
// Outputs
|
||||
emwr_rd_en, emrq_rd_en, emrr_access, emrr_write, emrr_datamode,
|
||||
emrr_ctrlmode, emrr_dstaddr, emrr_data, emrr_srcaddr, m_axi_awaddr,
|
||||
m_axi_awlen, m_axi_awsize, m_axi_awburst, m_axi_awcache,
|
||||
m_axi_awprot, m_axi_awqos, m_axi_awvalid, m_axi_wdata, m_axi_wstrb,
|
||||
m_axi_wlast, m_axi_wvalid, m_axi_bready, m_axi_araddr, m_axi_arlen,
|
||||
m_axi_arsize, m_axi_arburst, m_axi_arcache, m_axi_arprot,
|
||||
m_axi_arqos, m_axi_arvalid, m_axi_rready,
|
||||
emrr_ctrlmode, emrr_dstaddr, emrr_data, emrr_srcaddr, m_axi_awid,
|
||||
m_axi_awaddr, m_axi_awlen, m_axi_awsize, m_axi_awburst,
|
||||
m_axi_awlock, m_axi_awcache, m_axi_awprot, m_axi_awqos,
|
||||
m_axi_awvalid, m_axi_wid, m_axi_wdata, m_axi_wstrb, m_axi_wlast,
|
||||
m_axi_wvalid, m_axi_bready, m_axi_arid, m_axi_araddr, m_axi_arlen,
|
||||
m_axi_arsize, m_axi_arburst, m_axi_arlock, m_axi_arcache,
|
||||
m_axi_arprot, m_axi_arqos, m_axi_arvalid, m_axi_rready,
|
||||
// Inputs
|
||||
emwr_access, emwr_write, emwr_datamode, emwr_ctrlmode,
|
||||
emwr_dstaddr, emwr_data, emwr_srcaddr, emrq_access, emrq_write,
|
||||
emrq_datamode, emrq_ctrlmode, emrq_dstaddr, emrq_data,
|
||||
emrq_srcaddr, emrr_progfull, m_axi_aclk, m_axi_aresetn,
|
||||
m_axi_awready, m_axi_wready, m_axi_bresp, m_axi_bvalid,
|
||||
m_axi_arready, m_axi_rdata, m_axi_rresp, m_axi_rlast, m_axi_rvalid
|
||||
m_axi_awready, m_axi_wready, m_axi_bid, m_axi_bresp, m_axi_bvalid,
|
||||
m_axi_arready, m_axi_rid, m_axi_rdata, m_axi_rresp, m_axi_rlast,
|
||||
m_axi_rvalid
|
||||
);
|
||||
|
||||
parameter IDW = 12;
|
||||
|
||||
// fifo read-master port, writes from rx
|
||||
input emwr_access;
|
||||
@ -60,38 +62,55 @@ module emaxi(/*autoarg*/
|
||||
/*****************************/
|
||||
|
||||
input m_axi_aclk; // global clock signal.
|
||||
input m_axi_aresetn; // global reset singal. this signal is active low
|
||||
input m_axi_aresetn; // global reset singal.
|
||||
|
||||
//Write address channel
|
||||
output [IDW-1:0] m_axi_awid; // write address ID
|
||||
output [31 : 0] m_axi_awaddr; // master interface write address
|
||||
output [7 : 0] m_axi_awlen; // burst length. the burst length gives the exact number of transfers in a burst
|
||||
output [2 : 0] m_axi_awsize; // burst size. this signal indicates the size of each transfer in the burst
|
||||
output [1 : 0] m_axi_awburst; // burst type. the burst type and the size information;
|
||||
output [3 : 0] m_axi_awcache; // memory type. this signal indicates how transactions
|
||||
output [2 : 0] m_axi_awprot; // protection type. this signal indicates the privilege
|
||||
output [3 : 0] m_axi_awqos; // quality of service; qos identifier sent for each write transaction.
|
||||
output m_axi_awvalid; // write address valid.channel is signaling valid write address and control information.
|
||||
input m_axi_awready; // write address ready.the slave is ready to accept an address and associated control signals
|
||||
output [7 : 0] m_axi_awlen; // burst length.
|
||||
output [2 : 0] m_axi_awsize; // burst size.
|
||||
output [1 : 0] m_axi_awburst; // burst type.
|
||||
output [1 : 0] m_axi_awlock; // lock type
|
||||
output [3 : 0] m_axi_awcache; // memory type.
|
||||
output [2 : 0] m_axi_awprot; // protection type.
|
||||
output [3 : 0] m_axi_awqos; // quality of service
|
||||
output m_axi_awvalid; // write address valid
|
||||
input m_axi_awready; // write address ready
|
||||
|
||||
//Write data channel
|
||||
output [IDW-1:0] m_axi_wid;
|
||||
output [63 : 0] m_axi_wdata; // master interface write data.
|
||||
output [7 : 0] m_axi_wstrb; // write strobes.indicates which byte lanes hold valid data
|
||||
output m_axi_wlast; // write last. indicates the last transfer in a write burst.
|
||||
output m_axi_wvalid; // write valid. indicates that valid write data and strobes are available
|
||||
input m_axi_wready; // write ready. indicates that the slave can accept the write data.
|
||||
input [1 : 0] m_axi_bresp; // master interface write response. indicates the status of the write transaction.
|
||||
input m_axi_bvalid; // write response valid. channel is signaling a valid write response.
|
||||
output m_axi_bready; // response ready. indicates that master can accept write response.
|
||||
output [31 : 0] m_axi_araddr; // master interface read address. initial address of a read burst transaction.
|
||||
output [7 : 0] m_axi_arlen; // burst length. the burst length gives the exact number of transfers in a burst
|
||||
output [2 : 0] m_axi_arsize; // burst size. this signal indicates the size of each transfer in the burst
|
||||
output [1 : 0] m_axi_arburst; // burst type. the burst type and the size information;
|
||||
output [7 : 0] m_axi_wstrb; // byte write strobes
|
||||
output m_axi_wlast; // indicates last transfer in a write burst.
|
||||
output m_axi_wvalid; // indicates data is ready to go
|
||||
input m_axi_wready; // indicates that the slave is ready for data
|
||||
|
||||
//Write response channel
|
||||
input [IDW-1:0] m_axi_bid;
|
||||
input [1 : 0] m_axi_bresp; // status of the write transaction.
|
||||
input m_axi_bvalid; // channel is signaling a valid write response
|
||||
output m_axi_bready; // master can accept write response.
|
||||
|
||||
//Read address channel
|
||||
output [IDW-1:0] m_axi_arid; // read address ID
|
||||
output [31 : 0] m_axi_araddr; // initial address of a read burst
|
||||
output [7 : 0] m_axi_arlen; // burst length
|
||||
output [2 : 0] m_axi_arsize; // burst size
|
||||
output [1 : 0] m_axi_arburst; // burst type
|
||||
output [1 : 0] m_axi_arlock; //lock type
|
||||
output [3 : 0] m_axi_arcache; // memory type
|
||||
output [2 : 0] m_axi_arprot; // protection type
|
||||
output [3 : 0] m_axi_arqos; // qos identifier sent for each read transaction
|
||||
output m_axi_arvalid; // write address valid. channel is signaling valid read address and control information
|
||||
input m_axi_arready; // read address ready. indicates that slave is ready to accept an address
|
||||
output [3 : 0] m_axi_arqos; //
|
||||
output m_axi_arvalid; // valid read address and control information
|
||||
input m_axi_arready; // slave is ready to accept an address
|
||||
|
||||
//Read data channel
|
||||
input [IDW-1:0] m_axi_rid;
|
||||
input [63 : 0] m_axi_rdata; // master read data
|
||||
input [1 : 0] m_axi_rresp; // read response. indicates the status of the read transfer
|
||||
input m_axi_rlast; // read last. indicates the last transfer in a read burst
|
||||
input m_axi_rvalid; // read valid. channel is signaling the required read data
|
||||
output m_axi_rready; // read ready. indicates that master can accept the read data and response
|
||||
input [1 : 0] m_axi_rresp; // status of the read transfer
|
||||
input m_axi_rlast; // signals last transfer in a read burst
|
||||
input m_axi_rvalid; // signaling the required read data
|
||||
output m_axi_rready; // master can accept the readback data
|
||||
|
||||
//registers
|
||||
|
||||
@ -339,9 +358,9 @@ module emaxi(/*autoarg*/
|
||||
always @( posedge m_axi_aclk )
|
||||
if( ~m_axi_aresetn )
|
||||
begin
|
||||
emrr_data[31:0] <= 32'b0;
|
||||
emrr_srcaddr[31:0] <= 32'b0;
|
||||
emrr_access <= 1'b0;
|
||||
emrr_data[31:0] <= 32'b0;
|
||||
emrr_srcaddr[31:0] <= 32'b0;
|
||||
emrr_access <= 1'b0;
|
||||
end
|
||||
else
|
||||
begin
|
||||
|
||||
@ -5,130 +5,138 @@ module esaxi (/*autoarg*/
|
||||
emrq_datamode, emrq_ctrlmode, emrq_dstaddr, emrq_data,
|
||||
emrq_srcaddr, emrr_rd_en, mi_clk, mi_rx_emmu_sel, mi_tx_emmu_sel,
|
||||
mi_ecfg_sel, mi_embox_sel, mi_we, mi_addr, mi_din, s_axi_arready,
|
||||
s_axi_awready, s_axi_bresp, s_axi_bvalid, s_axi_rdata, s_axi_rlast,
|
||||
s_axi_rresp, s_axi_rvalid, s_axi_wready,
|
||||
s_axi_awready, s_axi_bid, s_axi_bresp, s_axi_bvalid, s_axi_rid,
|
||||
s_axi_rdata, s_axi_rlast, s_axi_rresp, s_axi_rvalid, s_axi_wready,
|
||||
// Inputs
|
||||
emwr_progfull, emrq_progfull, emrr_data, emrr_access, mi_ecfg_dout,
|
||||
mi_tx_emmu_dout, mi_rx_emmu_dout, mi_embox_dout, ecfg_tx_ctrlmode,
|
||||
ecfg_coreid, ecfg_timeout_enable, s_axi_aclk, s_axi_aresetn,
|
||||
s_axi_araddr, s_axi_arburst, s_axi_arcache, s_axi_arlen,
|
||||
s_axi_arprot, s_axi_arqos, s_axi_arsize, s_axi_arvalid,
|
||||
s_axi_awaddr, s_axi_awburst, s_axi_awcache, s_axi_awlen,
|
||||
s_axi_awprot, s_axi_awqos, s_axi_awsize, s_axi_awvalid,
|
||||
s_axi_bready, s_axi_rready, s_axi_wdata, s_axi_wlast, s_axi_wstrb,
|
||||
s_axi_arid, s_axi_araddr, s_axi_arburst, s_axi_arcache,
|
||||
s_axi_arlock, s_axi_arlen, s_axi_arprot, s_axi_arqos, s_axi_arsize,
|
||||
s_axi_arvalid, s_axi_awid, s_axi_awaddr, s_axi_awburst,
|
||||
s_axi_awcache, s_axi_awlock, s_axi_awlen, s_axi_awprot,
|
||||
s_axi_awqos, s_axi_awsize, s_axi_awvalid, s_axi_bready,
|
||||
s_axi_rready, s_axi_wid, s_axi_wdata, s_axi_wlast, s_axi_wstrb,
|
||||
s_axi_wvalid
|
||||
);
|
||||
|
||||
parameter [11:0] c_read_tag_addr = 12'h810;//emesh srcaddr tag
|
||||
parameter integer c_s_axi_addr_width = 30; //address width
|
||||
parameter [11:0] ELINKID = 12'h810;
|
||||
parameter IDW = 12;
|
||||
|
||||
/*****************************/
|
||||
/*Write request for TX fifo */
|
||||
/*****************************/
|
||||
output emwr_access;
|
||||
output emwr_write;
|
||||
output [1:0] emwr_datamode;
|
||||
output [3:0] emwr_ctrlmode;
|
||||
output [31:0] emwr_dstaddr;
|
||||
output [31:0] emwr_data;
|
||||
output [31:0] emwr_srcaddr;
|
||||
input emwr_progfull;
|
||||
output emwr_access;
|
||||
output emwr_write;
|
||||
output [1:0] emwr_datamode;
|
||||
output [3:0] emwr_ctrlmode;
|
||||
output [31:0] emwr_dstaddr;
|
||||
output [31:0] emwr_data;
|
||||
output [31:0] emwr_srcaddr;
|
||||
input emwr_progfull;
|
||||
|
||||
/*****************************/
|
||||
/*Read request for TX fifo */
|
||||
/*****************************/
|
||||
output emrq_access;
|
||||
output emrq_write;
|
||||
output [1:0] emrq_datamode;
|
||||
output [3:0] emrq_ctrlmode;
|
||||
output [31:0] emrq_dstaddr;
|
||||
output [31:0] emrq_data;
|
||||
output [31:0] emrq_srcaddr;
|
||||
input emrq_progfull; //TODO? used for?
|
||||
|
||||
output emrq_access;
|
||||
output emrq_write;
|
||||
output [1:0] emrq_datamode;
|
||||
output [3:0] emrq_ctrlmode;
|
||||
output [31:0] emrq_dstaddr;
|
||||
output [31:0] emrq_data;
|
||||
output [31:0] emrq_srcaddr;
|
||||
input emrq_progfull; //TODO? used for?
|
||||
|
||||
/*****************************/
|
||||
/*Read response from RX fifo */
|
||||
/*****************************/
|
||||
//Only data needed
|
||||
input [31:0] emrr_data;
|
||||
input emrr_access;
|
||||
output emrr_rd_en; //update read fifo
|
||||
|
||||
|
||||
input [31:0] emrr_data;
|
||||
input emrr_access;
|
||||
output emrr_rd_en; //update read fifo
|
||||
|
||||
|
||||
/*****************************/
|
||||
/*Register RD/WR Interface */
|
||||
/*****************************/
|
||||
output mi_clk;
|
||||
output mi_rx_emmu_sel;
|
||||
output mi_tx_emmu_sel;
|
||||
output mi_ecfg_sel;
|
||||
output mi_embox_sel;
|
||||
output mi_we;
|
||||
output [19:0] mi_addr;
|
||||
output [31:0] mi_din;
|
||||
input [31:0] mi_ecfg_dout;
|
||||
input [31:0] mi_tx_emmu_dout;
|
||||
input [31:0] mi_rx_emmu_dout;
|
||||
input [31:0] mi_embox_dout;
|
||||
output mi_clk;
|
||||
output mi_rx_emmu_sel;
|
||||
output mi_tx_emmu_sel;
|
||||
output mi_ecfg_sel;
|
||||
output mi_embox_sel;
|
||||
output mi_we;
|
||||
output [19:0] mi_addr;
|
||||
output [31:0] mi_din;
|
||||
input [31:0] mi_ecfg_dout;
|
||||
input [31:0] mi_tx_emmu_dout;
|
||||
input [31:0] mi_rx_emmu_dout;
|
||||
input [31:0] mi_embox_dout;
|
||||
|
||||
/*****************************/
|
||||
/*Config Settings */
|
||||
/*****************************/
|
||||
input [3:0] ecfg_tx_ctrlmode;
|
||||
input [11:0] ecfg_coreid;
|
||||
input ecfg_timeout_enable;
|
||||
input [3:0] ecfg_tx_ctrlmode;
|
||||
input [11:0] ecfg_coreid;
|
||||
input ecfg_timeout_enable;
|
||||
|
||||
/*****************************/
|
||||
/*AXI slave interface */
|
||||
/*****************************/
|
||||
//Clock and reset
|
||||
input s_axi_aclk;
|
||||
input s_axi_aresetn;
|
||||
input s_axi_aclk;
|
||||
input s_axi_aresetn;
|
||||
|
||||
//Read address channel
|
||||
input [31:0] s_axi_araddr;
|
||||
input [1:0] s_axi_arburst;
|
||||
input [3:0] s_axi_arcache;
|
||||
input [7:0] s_axi_arlen;
|
||||
input [2:0] s_axi_arprot;
|
||||
input [3:0] s_axi_arqos;
|
||||
output s_axi_arready;
|
||||
input [2:0] s_axi_arsize;
|
||||
input s_axi_arvalid;
|
||||
input [IDW-1:0] s_axi_arid; //write address ID
|
||||
input [31:0] s_axi_araddr;
|
||||
input [1:0] s_axi_arburst;
|
||||
input [3:0] s_axi_arcache;
|
||||
input [1:0] s_axi_arlock;
|
||||
input [7:0] s_axi_arlen;
|
||||
input [2:0] s_axi_arprot;
|
||||
input [3:0] s_axi_arqos;
|
||||
output s_axi_arready;
|
||||
input [2:0] s_axi_arsize;
|
||||
input s_axi_arvalid;
|
||||
|
||||
//Write address channel
|
||||
input [31:0] s_axi_awaddr;
|
||||
input [1:0] s_axi_awburst;
|
||||
input [3:0] s_axi_awcache;
|
||||
input [7:0] s_axi_awlen;
|
||||
input [2:0] s_axi_awprot;
|
||||
input [3:0] s_axi_awqos;
|
||||
output s_axi_awready;
|
||||
input [2:0] s_axi_awsize;
|
||||
input s_axi_awvalid;
|
||||
input [IDW-1:0] s_axi_awid; //write address ID
|
||||
input [31:0] s_axi_awaddr;
|
||||
input [1:0] s_axi_awburst;
|
||||
input [3:0] s_axi_awcache;
|
||||
input [1:0] s_axi_awlock;
|
||||
input [7:0] s_axi_awlen;
|
||||
input [2:0] s_axi_awprot;
|
||||
input [3:0] s_axi_awqos;
|
||||
input [2:0] s_axi_awsize;
|
||||
input s_axi_awvalid;
|
||||
output s_axi_awready;
|
||||
|
||||
|
||||
//Buffered write response channel
|
||||
input s_axi_bready;
|
||||
output [1:0] s_axi_bresp;
|
||||
output s_axi_bvalid;
|
||||
|
||||
output [IDW-1:0] s_axi_bid; //write address ID
|
||||
output [1:0] s_axi_bresp;
|
||||
output s_axi_bvalid;
|
||||
input s_axi_bready;
|
||||
|
||||
//Read channel
|
||||
output [31:0] s_axi_rdata;
|
||||
output s_axi_rlast;
|
||||
input s_axi_rready;
|
||||
output [1:0] s_axi_rresp;
|
||||
output s_axi_rvalid;
|
||||
|
||||
output [IDW-1:0] s_axi_rid; //write address ID
|
||||
output [31:0] s_axi_rdata;
|
||||
output s_axi_rlast;
|
||||
output [1:0] s_axi_rresp;
|
||||
output s_axi_rvalid;
|
||||
input s_axi_rready;
|
||||
|
||||
//Write channel
|
||||
input [31:0] s_axi_wdata;
|
||||
input s_axi_wlast;
|
||||
output s_axi_wready;
|
||||
input [3:0] s_axi_wstrb;
|
||||
input s_axi_wvalid;
|
||||
input [IDW-1:0] s_axi_wid; //write address ID
|
||||
input [31:0] s_axi_wdata;
|
||||
input s_axi_wlast;
|
||||
input [3:0] s_axi_wstrb;
|
||||
input s_axi_wvalid;
|
||||
output s_axi_wready;
|
||||
|
||||
// axi4full signals
|
||||
/*-------------------------BODY----------------------------------*/
|
||||
reg s_axi_awready;
|
||||
reg s_axi_wready;
|
||||
reg s_axi_bvalid;
|
||||
|
||||
Loading…
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Reference in New Issue
Block a user